On Tue, 2015-12-22 at 09:29 -0700, Jan Beulich wrote:
> > > > On 16.12.15 at 22:24, <andrew.coop...@citrix.com> wrote:
> > --- a/xen/include/public/arch-x86/featureset.h
> > +++ b/xen/include/public/arch-x86/featureset.h
> > @@ -163,6 +163,7 @@
> >
> > /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
> > #define X86_FEATURE_FSGSBASE ( 5*32+ 0) /* {RD,WR}{FS,GS}BASE
> > instructions */
> > +#define X86_FEATURE_TSC_ADJUST ( 5*32+ 1) /* TSC_ADJUST MSR
> > available */
>
> This would probably better go into patch 1.
Tools would then see this defined twice with only patch 1 applied, and
since the value is actually different I think the compiler will complain.
-#define X86_FEATURE_TSC_ADJUST 1 /* Tsc thread offset */
+#define X86_FEATURE_TSC_ADJUST ( 5*32+ 1) /* TSC_ADJUST MSR available */
The comment change seems to be a semantic one? Or was it wrong beofre?
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