Pass CPU features CLFLUSHOPT and CLWB into HVM domain so that those two instructions can be used by guest.
The specification of above two instructions can be found in https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Haozhong Zhang <haozhong.zh...@intel.com> --- tools/libxc/xc_cpufeature.h | 3 ++- tools/libxc/xc_cpuid_x86.c | 4 +++- xen/arch/x86/hvm/hvm.c | 7 +++++++ xen/include/asm-x86/cpufeature.h | 5 +++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h index c3ddc80..5288ac6 100644 --- a/tools/libxc/xc_cpufeature.h +++ b/tools/libxc/xc_cpufeature.h @@ -140,6 +140,7 @@ #define X86_FEATURE_RDSEED 18 /* RDSEED instruction */ #define X86_FEATURE_ADX 19 /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP 20 /* Supervisor Mode Access Protection */ - +#define X86_FEATURE_CLFLUSHOPT 23 /* CLFLUSHOPT instruction */ +#define X86_FEATURE_CLWB 24 /* CLWB instruction */ #endif /* __LIBXC_CPUFEATURE_H */ diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c index 8882c01..fecfd6c 100644 --- a/tools/libxc/xc_cpuid_x86.c +++ b/tools/libxc/xc_cpuid_x86.c @@ -426,7 +426,9 @@ static void xc_cpuid_hvm_policy(xc_interface *xch, bitmaskof(X86_FEATURE_RDSEED) | bitmaskof(X86_FEATURE_ADX) | bitmaskof(X86_FEATURE_SMAP) | - bitmaskof(X86_FEATURE_FSGSBASE)); + bitmaskof(X86_FEATURE_FSGSBASE) | + bitmaskof(X86_FEATURE_CLWB) | + bitmaskof(X86_FEATURE_CLFLUSHOPT)); } else regs[1] = 0; regs[0] = regs[2] = regs[3] = 0; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 21470ec..58c83a5 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4598,6 +4598,13 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, /* Don't expose INVPCID to non-hap hvm. */ if ( (count == 0) && !hap_enabled(d) ) *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); + + if ( (count == 0) && !cpu_has_clflushopt ) + *ebx &= ~cpufeat_mask(X86_FEATURE_CLFLUSHOPT); + + if ( (count == 0) && !cpu_has_clwb ) + *ebx &= ~cpufeat_mask(X86_FEATURE_CLWB); + break; case 0xb: /* Fix the x2APIC identifier. */ diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index ef96514..5818228 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -162,6 +162,8 @@ #define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */ #define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ +#define X86_FEATURE_CLFLUSHOPT (7*32+23) /* CLFLUSHOPT instruction */ +#define X86_FEATURE_CLWB (7*32+24) /* CLWB instruction */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 8 */ #define X86_FEATURE_PKU (8*32+ 3) /* Protection Keys for Userspace */ @@ -234,6 +236,9 @@ #define cpu_has_xgetbv1 boot_cpu_has(X86_FEATURE_XGETBV1) #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) +#define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT) +#define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) + enum _cache_type { CACHE_TYPE_NULL = 0, CACHE_TYPE_DATA = 1, -- 2.4.8 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
