On Thu, Nov 26, 2015 at 12:11 AM, Dietmar Hahn <dietmar.h...@ts.fujitsu.com>
wrote:
> Am Dienstag 24 November 2015, 15:53:12 schrieb Brendan Gregg:
> > This introduces a way to have a restricted VPMU, by specifying one of two
> > predefined groups of PMCs to make available. For secure environments,
> this
> > allows the VPMU to be used without needing to enable all PMCs.
> >
> > Signed-off-by: Brendan Gregg <bgr...@netflix.com>
> > ---
> > docs/misc/xen-command-line.markdown | 14 +++++++++-
> > xen/arch/x86/cpu/vpmu.c | 51
> +++++++++++++++++++++++++++++--------
> > xen/arch/x86/cpu/vpmu_intel.c | 48
> ++++++++++++++++++++++++++++++++++
> > xen/include/asm-x86/msr-index.h | 1 +
> > xen/include/public/pmu.h | 14 ++++++++--
> > 5 files changed, 115 insertions(+), 13 deletions(-)
> >
> > diff --git a/docs/misc/xen-command-line.markdown
> b/docs/misc/xen-command-line.markdown
> > index 70daa84..6055a68 100644
> > --- a/docs/misc/xen-command-line.markdown
> > +++ b/docs/misc/xen-command-line.markdown
> > @@ -1452,7 +1452,7 @@ Use Virtual Processor ID support if available.
> This prevents the need for TLB
> > flushes on VM entry and exit, increasing performance.
> >
> > ### vpmu
> > -> `= ( bts )`
> > +> `= ( <boolean> | { bts | ipc | arch [, ...] } )`
> >
> > > Default: `off`
> >
> > @@ -1468,6 +1468,18 @@ wrong behaviour (see handle\_pmc\_quirk()).
> > If 'vpmu=bts' is specified the virtualisation of the Branch Trace Store
> (BTS)
> > feature is switched on on Intel processors supporting this feature.
> >
> > +vpmu=ipc enables performance monitoring, but restricts the counters to
> the
> > +most minimum set possible: instructions, cycles, and reference cycles.
> These
> > +can be used to calculate instructions per cycle (IPC).
> > +
> > +vpmu=arch enables performance monitoring, but restricts the counters to
> the
> > +pre-defined architectural events only. These are exposed by cpuid, and
> listed
> > +in Table 18-1 from the Intel 64 and IA-32 Architectures Software
> Developer's
> > +Manual, Volume 3B, System Programming Guide, Part 2.
>
> Maybe you better should write
> section "Pre-defined Architectural Performance Events"
> instead of "Table 18-1" because the number may change in the document.
> And below in the comment of the code too.
>
Ah, thanks, yes, otherwise it'd be pretty confusing if it changed and I was
pointing people to the wrong table.
Brendan
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