> From: Jan Beulich [mailto:jbeul...@suse.com] > Sent: Tuesday, November 24, 2015 4:52 PM > > >>> On 24.11.15 at 08:56, <kevin.t...@intel.com> wrote: > >> From: Wu, Feng > >> Sent: Tuesday, November 24, 2015 3:54 PM > >> > From: Tian, Kevin > >> > Sent: Tuesday, November 24, 2015 3:45 PM > >> > > + /* Setup/Update interrupt remapping table entry. */ > >> > > + setup_posted_irte(&new_ire, &old_ire, pi_desc, gvec); > >> > > + ret = cmpxchg16b(p, &old_ire, &new_ire); > >> > > + > >> > > + /* > >> > > + * In the above, we use cmpxchg16 to atomically update the 128-bit > >> > IRTE, > >> > > + * and the hardware cannot update the IRTE behind us, so the > >> > > return > >> > value > >> > > >> > hardware can DEFINITELY update IRTE behind us, right? e.g. after the IRTE > >> > entry > >> > is fully up, when interrupt is posted, etc. Here you might mean hardware > >> > cannot > >> > update the IRTE at this point? > >> > >> Yes, you description above is more accurate. But why hardware needs to > >> update IRTE when interrupt is posted? I think it needs to update the > >> posted interrupt descriptor when posting an interrupt, not the IRTE, > >> right? > > > > sorry mess IRTE and posted descriptor together. but using "behind" > > is still not accurate to state your point here. :-) > > Well, "behind us" and "behind our back" seem to mean mostly the > same to me. >
Thanks for confirming language part. Then I'm OK with it. Thanks Kevin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
