On Wed, 2015-11-11 at 12:49 +0000, Julien Grall wrote:
>
> > + if ( s->enabled )
> > + gicv2_irq_disable(desc);
>
> Don't we want to disable the IRQ first and then saving the state?
We need at least the enable/disable state first. Perhaps some of the other
stuff might be better done afterwards, I'll have a think.
> >
> > +static void gicv3_save_and_mask_hwppi(struct irq_desc *desc,
> > + struct hwppi_state *s)
> > +{
> > + const unsigned int mask = (1u << desc->irq);
> > + const unsigned int pendingr = readl_relaxed(GICD_RDIST_SGI_BASE +
> > GICR_ISPENDR);
> > + const unsigned int activer = readl_gicd(GICD_RDIST_SGI_BASE +
> > GICR_ISACTIVER);
> > + const unsigned int enabler = readl_gicd(GICD_RDIST_SGI_BASE +
> > GICR_ISENABLER);
>
> Those registers don't exists. Did you try to build the GICv3 code?
I thought so (and was a bit surprised there were apparently all the right
defines in place). But actually I was building for arm32 and had forgotten
that doesn't build gicv3.
Ian.
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