>>> On 22.10.15 at 16:40, <haozhong.zh...@intel.com> wrote: > On Thu, Oct 22, 2015 at 06:53:27AM -0600, Jan Beulich wrote: >> >>> On 28.09.15 at 09:13, <haozhong.zh...@intel.com> wrote: >> > --- a/xen/include/asm-x86/hvm/svm/svm.h >> > +++ b/xen/include/asm-x86/hvm/svm/svm.h >> > @@ -96,6 +96,7 @@ extern u32 svm_feature_flags; >> > >> > /* TSC rate */ >> > #define DEFAULT_TSC_RATIO 0x0000000100000000ULL >> > +#define MAX_TSC_RATIO 0x000000ffffffffffULL >> > #define TSC_RATIO_RSVD_BITS 0xffffff0000000000ULL >> >> How about >> >> #define MAX_TSC_RATIO (~TSC_RATIO_RSVD_BITS) > > Yes. > >> ? (But of course it's not really clear in which way this is to >> be used as "maximum" without seeing the code using it. I.e. >> it's not clear whether you don't really just mean to specify >> all the valid bits in the MSR.) > > The reserved bits are used to calculate the maximum TSC ratio which is > used in hvm_setup_tsc_scaling() in patch 4 to check the whether a TSC > scaling ratio is legal.
The main motivation behind the comment was to understand whether one of the two constants wouldn't suffice. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
