On 09/16/2015 03:46 PM, Wei Liu wrote:
On Wed, Sep 16, 2015 at 09:47:51AM +0100, Ross Lagerwall wrote:
Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
log-dirty"), the A and D bits of EPT paging entries are set
unconditionally, regardless of whether PML is enabled or not. This
causes a regression in Xen 4.6 on some processors due to Intel Errata
AVR41 -- HVM guests get severe memory corruption when the A bit is
set. The errata affects the Atom C2000 family (Avaton).
Instead, only set the bits if PML is enabled.
I think we need to make clear that this is working around hardware issue
because there is nothing fundamentally wrong with setting those bits?
I.e. I want to distinguish bug fix from workaround, this would certainly
affect the judgement on this patch.
It is a workaround for a hardware issue, but the issue has been exposed
due to changes in Xen 4.6, so it is still a regression compared with Xen
4.5.
Correct me if I'm wrong. Do you not need to disallow using PML on such
platform? What would happen with your patch on a broken platform that
has PML enabled? I think PML wouldn't work, xen is broken in another
way, but user won't get any visibility why it doesn't work, which is not
nice.
As far as I know, the errata only affects processors which don't
actually support PML, so it wouldn't be possible to enable PML anyway.
--
Ross Lagerwall
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