This patch adds cmpxchg16b support for x86-64, so software
can perform 128-bit atomic write/read.
CC: Keir Fraser <k...@xen.org>
CC: Jan Beulich <jbeul...@suse.com>
CC: Andrew Cooper <andrew.coop...@citrix.com>
Signed-off-by: Feng Wu <feng...@intel.com>
---
v4:
- Use pointer as the parameter of __cmpxchg16b().
- Use gcc's __uint128_t built-in type
- Make the parameters of __cmpxchg16b() void *
v3:
- Newly added.
xen/include/asm-x86/x86_64/system.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/xen/include/asm-x86/x86_64/system.h
b/xen/include/asm-x86/x86_64/system.h
index 662813a..0267797 100644
--- a/xen/include/asm-x86/x86_64/system.h
+++ b/xen/include/asm-x86/x86_64/system.h
@@ -6,6 +6,38 @@
(unsigned long)(n),sizeof(*(ptr))))
/*
+ * Atomic 16 bytes compare and exchange. Compare OLD with MEM, if
+ * identical, store NEW in MEM. Return the initial value in MEM.
+ * Success is indicated by comparing RETURN with OLD.
+ *
+ * This function can only be called when cpu_has_cx16 is ture.
+ */
+
+static always_inline __uint128_t __cmpxchg16b(
+ volatile void *ptr, void *old, void *new)
+{
+ uint64_t prev_high, prev_low;
+ uint64_t new_high = (*(__uint128_t *)new) >> 64;
+ uint64_t new_low = (uint64_t)(*(__uint128_t *)new);
+ uint64_t old_high = (*(__uint128_t *)old) >> 64;
+ uint64_t old_low = (uint64_t)(*(__uint128_t *)old);
+
+ ASSERT(cpu_has_cx16);
+
+ asm volatile ( "lock; cmpxchg16b %4"
+ : "=d" (prev_high), "=a" (prev_low)
+ : "c" (new_high), "b" (new_low),
+ "m" (*__xg((volatile void *)ptr)),
+ "0" (old_high), "1" (old_low)
+ : "memory" );
+
+ return ( ((__uint128_t)prev_high) << 64 | prev_low );
+}
+
+#define cmpxchg16b(ptr,o,n) \
+ __cmpxchg16b((ptr), (__uint128_t *)(o), (__uint128_t *)(n))
+
+/*
* This function causes value _o to be changed to _n at location _p.
* If this access causes a fault then we return 1, otherwise we return 0.
* If no fault occurs then _o is updated to the value we saw at _p. If this
--
2.1.0
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