>>> On 24.06.15 at 07:18, <feng...@intel.com> wrote:
> @@ -1698,13 +1700,35 @@ static void vmx_deliver_posted_intr(struct vcpu *v,
> u8 vector)
> */
> pi_set_on(&v->arch.hvm_vmx.pi_desc);
> }
> - else if ( !pi_test_and_set_on(&v->arch.hvm_vmx.pi_desc) )
> + else
> {
> + prev.control = 0;
> +
> + do {
> + old.control = v->arch.hvm_vmx.pi_desc.control &
> + ~(1 << POSTED_INTR_ON | 1 << POSTED_INTR_SN);
> + new.control = v->arch.hvm_vmx.pi_desc.control |
> + 1 << POSTED_INTR_ON;
> +
> + /*
> + * Currently, we don't support urgent interrupt, all
> + * interrupts are recognized as non-urgent interrupt,
> + * so we cannot send posted-interrupt when 'SN' is set.
> + * Besides that, if 'ON' is already set, we cannot set
> + * posted-interrupts as well.
> + */
> + if ( prev.sn || prev.on )
> + {
> + vcpu_kick(v);
> + return;
> + }
> +
> + prev.control = cmpxchg(&v->arch.hvm_vmx.pi_desc.control,
> + old.control, new.control);
> + } while ( prev.control != old.control );
This pretty clearly demonstrates that mixing bitfields and non-bitfield
mask operations makes code hard to read: How is one supposed to
see at the first glance that e.g. prev.on and
old.control & (1 << POSTED_INTR_ON) are the same thing?
Jan
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