> From: Wu, Feng > Sent: Wednesday, July 08, 2015 7:52 PM > > > > > + * - For lowest-priority interrupts, we find the destination vCPU > > > > > from the > > > > > + * guest vector using vector-hashing mechanism and return true. > > > > > This > > > > follows > > > > > + * the hardware behavior, since modern Intel CPUs use vector > > hashing to > > > > > + * handle the lowest-priority interrupt. > > > > > > > > Does AMD use same hashing mechanism? Can this interface be reused by > > > > other IOMMU type or it's an Intel specific implementation? > > > > > > I am not sure how AMD handle lowest-priority. Intel hardware guys told me > > > recent Intel hardware platform use this method to deliver lowest-priority > > > interrupts. What do you mean by "other IOMMU type"? > > > > > > > OS doesn't assume how vector hashing is done in hardware level. So it should > > be fine to use Intel algorithm in this emulation path. However my point is > > just > > about the comment " since modern Intel CPUs use vector hashing to handle > > the lowest-priority interrupt". It's not because Intel does so. It's the > > implementation option that you choose Intel algorithm here. > > here I can mention: we choose vector-hashing for lowest-priority handling and > list Intel as an example to use it, okay? >
Yes. :-) Thanks Kevin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
