>>> On 26.06.15 at 12:37, <ian.campb...@citrix.com> wrote: > At Andy Cooper's request I ran a quick job with mtrr.show=true > http://logs.test-lab.xenproject.org/osstest/logs/58909/ > > I think the relevant serial output is: > Jun 26 09:57:42.325077 (XEN) MTRR default type: uncachable > Jun 26 09:57:42.325111 (XEN) MTRR fixed ranges enabled: > Jun 26 09:57:42.333068 (XEN) 00000-9ffff write-back > Jun 26 09:57:42.333101 (XEN) a0000-bffff uncachable > Jun 26 09:57:42.333128 (XEN) c0000-fffff write-back > Jun 26 09:57:42.341077 (XEN) MTRR variable ranges enabled: > Jun 26 09:57:42.341110 (XEN) 0 base 000000000000 mask ffff80000000 > write-back > Jun 26 09:57:42.349088 (XEN) 1 base 000080000000 mask ffffc0000000 > write-back > Jun 26 09:57:42.349124 (XEN) 2 disabled > Jun 26 09:57:42.357068 (XEN) 3 disabled > Jun 26 09:57:42.357098 (XEN) 4 disabled > Jun 26 09:57:42.357122 (XEN) 5 disabled > Jun 26 09:57:42.357147 (XEN) 6 disabled > Jun 26 09:57:42.365063 (XEN) 7 disabled
This alone would mean UC for all memory above 4G. But I seem to recall AMD having some mechanism to avoid using MTRRs for this case. Let me try to dig this out once back from lunch. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
