Hi Ian, On 27/03/15 14:33, Ian Campbell wrote: > Previously we implemented all registers as RAZ/WI even if they > shouldn't be accessible to userspace. > > It is not entirely clear whether attempts to access *_EL1 registers > from EL0 will trap to EL1 or EL2, be conservative and treat as an > undef injection. > > PMUSERENR_EL0 and MDCCSR_EL0 are R/O to EL0. MDCCSR_EL0 was previously > not handled at all. > > Other PM*_EL0 registers are accessible at EL0 only if PMUSERENR_EL0.EN > is set, since we emulate that as RAZ/WI we know that bit cannot be > set. > > Signed-off-by: Ian Campbell <ian.campb...@citrix.com> Reviewed-by: Julien Grall <julien.gr...@linaro.org>
Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
