>>> Roger Pau Monné <roger....@citrix.com> 09/18/17 7:21 PM >>> >On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote: >> +## Hardware perspective >> + >> + MBA defines a range of MSRs to support specifying a delay value (Thrtl) >> per >> + COS, with details below. >> + >> + ``` >> + +----------------------------+----------------+ >> + | MSR (per socket) | Address | >> + +----------------------------+----------------+ >> + | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 | >> + +----------------------------+----------------+ >> + | ... | ... | >> + +----------------------------+----------------+ >> + | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n | >> + +----------------------------+----------------+ >> + ``` >> + >> + When context switch happens, the COS ID of domain is written to >> per-thread MSR >> + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation >> according > >I think this is missing some context of the relation between a thread >and the MSR. I assume it's related to IA32_PQR_ASSOC, but I have no >idea what that constant means. > >What's more, Xen doesn't have threads, so you should maybe speak about >vCPUs instead?
I think talk is of hardware aspects here, i.e. "thread" as in "hyper-thread". Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
