>>> On 21.08.17 at 13:55, <andrew.coop...@citrix.com> wrote:
> This avoids unnecessary updates to the stack shadow copy of cr4 during
> critical regions with interrupts disabled.
Hmm, yes - we don't access CR4 in #MC or NMI handling, do we?
> No change in behaviour.
>
> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
with ...
> --- a/xen/arch/x86/flushtlb.c
> +++ b/xen/arch/x86/flushtlb.c
> @@ -81,9 +81,14 @@ void write_cr3(unsigned long cr3)
>
> hvm_flush_guest_tlbs();
>
> - write_cr4(cr4 & ~X86_CR4_PGE);
> - asm volatile ( "mov %0, %%cr3" : : "r" (cr3) : "memory" );
> - write_cr4(cr4);
> + asm volatile ("mov %[npge], %%cr4;"
> + "mov %[cr3], %%cr3;"
> + "mov %[cr4], %%cr4;"
> + ::
> + [npge] "r" (cr4 & ~X86_CR4_PGE),
> + [cr3] "r" (cr3),
> + [cr4] "r" (cr4)
> + : "memory");
... blanks added immediately inside the parentheses here and ...
> @@ -123,9 +128,11 @@ unsigned int flush_area_local(const void *va, unsigned
> int flags)
>
> hvm_flush_guest_tlbs();
>
> - write_cr4(cr4 & ~X86_CR4_PGE);
> - barrier();
> - write_cr4(cr4);
> + asm volatile ("mov %[npge], %%cr4;"
> + "mov %[cr4], %%cr4;"
> + ::
> + [npge] "r" (cr4 & ~X86_CR4_PGE),
> + [cr4] "r" (cr4));
... here.
Jan
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