On 14/08/17 15:39, Boris Ostrovsky wrote:
+#define spin_lock_kick(l) \
+({ \to understand why
you need a stronger one here
+ smp_mb(); \
arch_lock_signal() has already a barrier for ARM. So we have a double
barrier now.
However, the barrier is slightly weaker (smp_wmb()). I am not sure why
you need to use a stronger barrier here. What you care is the write to
be done before signaling, read does not much matter. Did I miss anything?
Yes, smp_wmb() should be sufficient.
Should I then add arch_lock_signal_wmb() --- defined as
arch_lock_signal() for ARM and smp_wmb() for x86?
I am not an x86 expert. Do you know why the barrier is not in
arch_lock_signal() today?
-boris
Cheers,
+ arch_lock_signal(); \
+})
+
/* Ensure a lock is quiescent between two critical operations. */
#define spin_barrier(l) _spin_barrier(l)
--
Julien Grall
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