On Wed, 25 Feb 2015, Frediano Ziglio wrote:
> The GICH in this platform is mainly compatible with the standard
> GICv2 beside APR and LR register offsets.
>
> Signed-off-by: Frediano Ziglio <frediano.zig...@huawei.com>
> ---
> xen/arch/arm/gic-hip04.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
> index 9a7ed46..a1ae520 100644
> --- a/xen/arch/arm/gic-hip04.c
> +++ b/xen/arch/arm/gic-hip04.c
> @@ -88,6 +88,11 @@ static DEFINE_PER_CPU(u16, gic_cpu_id);
> #undef GICD_SGI_TARGET_SHIFT
> #define GICD_SGI_TARGET_SHIFT 8
>
> +#undef GICH_APR
> +#undef GICH_LR
> +#define GICH_APR 0x70
> +#define GICH_LR 0x80
> +
> static inline void writeb_gicd(uint8_t val, unsigned int offset)
> {
> writeb_relaxed(val, gicv2.map_dbase + offset);
You can fold these changes in the first patch. Please use a clear naming
scheme that doesn't collide with GICv2 names.
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