>>> On 19.04.17 at 21:33, <chao....@intel.com> wrote: > On Wed, Apr 19, 2017 at 03:41:41PM +0800, Chao Gao wrote: >>>> - vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE | >>>> - APIC_DEFAULT_PHYS_BASE); >>>> + vlapic->hw.apic_base_msr |= APIC_DEFAULT_PHYS_BASE; >>> >>>Perhaps better move this ahead of the call to vlapic_reset() then >>>too. >>> >>>Remains the question (not answered by the SDM afaics): What >>>happens to the base address during reset? >> >>Actually, I don't know and that's also why I don't touch apic_base_msr in the >>first verson. Will try to get a confirmation from hardware guys. > > According to the description about APIC base address in > "ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) -> > "LOCAL APIC" -> "Local APIC Status and Location", the APIC base > address is set to 0xFEE00000H as a result of reset or power-up.
Ah, yes - not very helpful for the different pieces of reset state to be scattered across the document. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org https://lists.xen.org/xen-devel
