Hi Ian, The issue observed on credit2 scheduler is similar to the rt scheduler on arm platform. The root cause is that interrupts are disabled in the beginning of arm context_switch, thus spin_lock_irq is failing in ASSERT(local_irq_is_enabled()). I propose to change both credit2 and rt scheduler to run on arm platform as well and re-run the regression with scheduler patches.
On Sat, Jan 31, 2015 at 12:50 PM, Ian Campbell <ian.campb...@citrix.com> wrote: > On Fri, 2015-01-30 at 18:19 +0200, Denys Drozdov wrote: > > > since context_save executed right from IRQ level. The arm interrupt > > handling differs from x86. ARM is handling context_saved with IRQ > > disabled in CPSR, though x86 has IRQs on. Thus it is failing on ASSERT > > inside spin_lock_irq when running on ARM. I guess it should work on > > x86, so this issue is ARM platform specific. > > FWIW I was waiting for it to happen to a xen-unstable run but the latest > osstest gate run at > http://www.chiark.greenend.org.uk/~xensrcts/logs/33915/ which included > Dario's patches to rationalize the schedulr tests vs. archs also > resulted in a similar sounding failure on credit2: > > http://www.chiark.greenend.org.uk/~xensrcts/logs/33915/test-armhf-armhf-xl-credit2/info.html > > http://www.chiark.greenend.org.uk/~xensrcts/logs/33915/test-armhf-armhf-xl-credit2/serial-marilith-n5.txt > > [Thu Jan 29 13:29:28 2015](XEN) Assertion 'local_irq_is_enabled()' > failed at spinlock.c:137 > [Thu Jan 29 13:29:28 2015](XEN) ----[ Xen-4.6-unstable arm32 > debug=y Not tainted ]---- > [Thu Jan 29 13:29:28 2015](XEN) CPU: 0 > [Thu Jan 29 13:29:28 2015](XEN) PC: 00229734 > _spin_lock_irq+0x18/0x94 > [Thu Jan 29 13:29:28 2015](XEN) CPSR: 200000da MODE:Hypervisor > [Thu Jan 29 13:29:28 2015](XEN) R0: 4000823c R1: 00000000 R2: > 02faf080 R3: 600000da > [Thu Jan 29 13:29:28 2015](XEN) R4: 4000823c R5: 4000d000 R6: > 4000823c R7: 002ee020 > [Thu Jan 29 13:29:28 2015](XEN) R8: 4000f218 R9: 00000000 > R10:0026fe08 R11:7ffcfefc R12:00000002 > [Thu Jan 29 13:29:28 2015](XEN) HYP: SP: 7ffcfeec LR: 0021f34c > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) VTCR_EL2: 80003558 > [Thu Jan 29 13:29:28 2015](XEN) VTTBR_EL2: 00010002b9ffc000 > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) SCTLR_EL2: 30cd187f > [Thu Jan 29 13:29:28 2015](XEN) HCR_EL2: 000000000038643f > [Thu Jan 29 13:29:28 2015](XEN) TTBR0_EL2: 00000000ff6e8000 > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) ESR_EL2: 00000000 > [Thu Jan 29 13:29:28 2015](XEN) HPFAR_EL2: 0000000000000000 > [Thu Jan 29 13:29:28 2015](XEN) HDFAR: 00000000 > [Thu Jan 29 13:29:28 2015](XEN) HIFAR: 00000000 > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) Xen stack trace from sp=7ffcfeec: > [Thu Jan 29 13:29:28 2015](XEN) 0024d068 00000000 002f0328 > 7ffcff2c 0021f34c 00000000 00000000 6591e5c1 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 4000d000 4000d000 > 00000000 00000000 00000000 00000000 7ffcff3c > [Thu Jan 29 13:29:28 2015](XEN) 002285dc 00007fff 00000000 > 7ffcff4c 00242614 00000000 00000000 7ffcff54 > [Thu Jan 29 13:29:28 2015](XEN) 002427c8 00000000 00242b6c > 00000000 ffffffff 28000000 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 00000000 27a00000 > 000001d3 00000000 00000000 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 00000000 00000000 > 00000000 00000000 00000000 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) 00000000 00000000 00000000 > 00000000 00000000 > [Thu Jan 29 13:29:28 2015](XEN) Xen call trace: > [Thu Jan 29 13:29:28 2015](XEN) [<00229734>] > _spin_lock_irq+0x18/0x94 (PC) > [Thu Jan 29 13:29:28 2015](XEN) [<0021f34c>] > csched2_context_saved+0x44/0x18c (LR) > [Thu Jan 29 13:29:28 2015](XEN) [<0021f34c>] > csched2_context_saved+0x44/0x18c > [Thu Jan 29 13:29:28 2015](XEN) [<002285dc>] > context_saved+0x58/0x80 > [Thu Jan 29 13:29:28 2015](XEN) [<00242614>] > schedule_tail+0x148/0x2f0 > [Thu Jan 29 13:29:28 2015](XEN) [<002427c8>] > continue_new_vcpu+0xc/0x70 > [Thu Jan 29 13:29:28 2015](XEN) [<00242b6c>] > context_switch+0x74/0x7c > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) > [Thu Jan 29 13:29:28 2015](XEN) > **************************************** > [Thu Jan 29 13:29:28 2015](XEN) Panic on CPU 0: > [Thu Jan 29 13:29:28 2015](XEN) Assertion 'local_irq_is_enabled()' > failed at spinlock.c:137 > [Thu Jan 29 13:29:28 2015](XEN) > **************************************** > > I didn't have a chance yet to think about whether the ARM ctxt switch or > the scheduler(s) are in the wrong here... > > Ian. > > > -- Denis Drozdov <http://www.globallogic.com/email_disclaimer.txt>
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