>>> On 15.01.15 at 18:28, <edmund.h.wh...@intel.com> wrote: > On 01/15/2015 12:16 AM, Jan Beulich wrote: >>>>> On 14.01.15 at 18:35, <edmund.h.wh...@intel.com> wrote: >>> Right. The key observation is that at any single point in time, a given >>> hardware thread can be fetching an instruction or reading data, but not >>> both. >> >> Fine, as long as an instruction reading itself isn't going to lead to >> a live lock. > > That's not how the hardware works. By the time you figure out that the > instruction you are executing reads memory, the instruction itself has > been fetched and decoded. That won't happen again during this execution. > > That's true for every CPU I've ever seen, not just Intel ones.
Certainly not if either the fetch or the data read faults/vmexits. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
