On 12/1/2023 12:32 PM, Viresh Kumar wrote:
On 01-12-23, 12:05, Haixu Cui wrote:
Looks good. Will update as follows:
\field{tx_nbits_supported} and \field{rx_nbits_supported} indicate the
different n-bit transfer modes supported by the device, for writing and
reading respectively. SINGLE is always supported. A set bit here indicates
that the corresponding n-bit transfer is supported, otherwise not:
bit 0: DUAL;
bit 1: QUAD;
bit 2: OCTAL;
other bits are reserved and must be set as 0 by the device.
Note: Transfer bit options are commonly used in SPI:
Maybe:
Note: The commonly used SPI transfer modes are:
Hi Viresh,
SPI transfer modes here may cause misunderstanding, in Wikipedia,
SPI mode is the combinations of clock polarity and clock phases:
https://en.wikipedia.org/w/index.php?title=Serial_Peripheral_Interface&action=edit§ion=4
What about updating as: "Note: The commonly used SPI n-bit transfer
options are:"
Thanks & BR
Haixu Cui
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