On Tue, 25 Oct 2016 21:19:15 +0000
"Haynal, Steve" <steve_hay...@mentor.com> wrote:
> Hi Ard,
>
> Yes, I noted that message in my first e-mail too. I may be able to reduce the
> size of the region to something that will work on aarch64. But even for
> another device that has a single small (16kB) memory region, that region
> shows up as disabled in lspci on aarch64 but not so on x86. There are no
> drivers in either case. Any ideas on why it shows up as disabled on aarch64?
>
This was in your original post:
x86:
00:09.0 Memory controller: Xilinx Corporation Device 7022
Subsystem: Xilinx Corporation Device 0007
Physical Slot: 9
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at e0071000 (32-bit, non-prefetchable) [size=4K]
Region 1: Memory at c0000000 (32-bit, non-prefetchable)
[size=512M]
aarch64:
00:09.0 Memory controller: Xilinx Corporation Device 7022
Subsystem: Xilinx Corporation Device 0007
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 47
Region 0: Memory at 10000000 (32-bit, non-prefetchable)
[disabled] [size=4K]
Region 1: Memory at <ignored> (32-bit, non-prefetchable)
[disabled]
Note the Mem- vs Mem+. If you flip that with setpci (setpci -s 00:09.0
COMMAND=2:2), it'll show at least BAR0 as enabled. Maybe it was left
disabled since not all the resources were allocated.
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