Ok , I will look it up . But its seems that there is a fifo that waits until there is a full burst and just then release data from the dma- master . If i'm right, where can i find it ?
בתאריך יום א׳, 4 באוק׳ 2020 ב-20:01 מאת Jonathon Pendlum < jonathon.pend...@ettus.com>: > Hi Daniel, > > The latency will be dominated by Xilinx's MIG IP that interfaces with the > DDR RAM. You can try looking at Xilinx's documentation and see what > parameters you can change to improve latency. > > Jonathon > > On Sat, Oct 3, 2020 at 9:10 AM Daniel Ozer via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi everyone, >> I'm working on usrp x310 . >> I create my own version of the replay block . >> I almost didn't change anything in the 2 state machines in the >> axi_replay.v . >> everything worked fine but then i saw in the chipscope that my replay >> block got data after 110 clks. (although the read ctrl ports indicate that >> the ddr start processing my read request ) >> Is there any reason it takes 110clks to get the first data from a burst ? >> How can I lower this high latency ? >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
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