Hi Folks, I'm in the midst of building the fpga code for the x310 on master. I'm building on a 24-thread xeon with plenty of memory. Is there a magic flag, setting, etc that enables parallelism in generating the ip (the invocations of viv_generate_ip.tcl)?? I tried make -j4 to no avail.
I really like how the build system regenerates the ip for different families and part numbers. NIcely done! Thanks! Eric
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