Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3_AR71898 (lin64) Build 2405991 Thu Dec  6 23:36:41 MST 2018
| Date         : Fri Jan 31 14:20:50 2020
| Host         : pratthpc.crc.nd.edu running 64-bit Red Hat Enterprise Linux Server release 7.7 (Maipo)
| Command      : report_utilization -omit_locs -file /afs/crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build-N310_RFNOC_XG/build.rpt
| Design       : n3xx
| Device       : 7z100ffg900-2
| Design State : Routed
----------------------------------------------------------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+--------+-----------+-------+
|          Site Type         |  Used  | Available | Util% |
+----------------------------+--------+-----------+-------+
| Slice LUTs                 | 193671 |    277400 | 69.82 |
|   LUT as Logic             | 163406 |    277400 | 58.91 |
|   LUT as Memory            |  30265 |    108200 | 27.97 |
|     LUT as Distributed RAM |  11018 |           |       |
|     LUT as Shift Register  |  19247 |           |       |
| Slice Registers            | 322013 |    554800 | 58.04 |
|   Register as Flip Flop    | 321999 |    554800 | 58.04 |
|   Register as Latch        |      0 |    554800 |  0.00 |
|   Register as AND/OR       |     14 |    554800 | <0.01 |
| F7 Muxes                   |   4779 |    138700 |  3.45 |
| F8 Muxes                   |   1798 |     69350 |  2.59 |
+----------------------------+--------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+--------+--------------+-------------+--------------+
|  Total | Clock Enable | Synchronous | Asynchronous |
+--------+--------------+-------------+--------------+
| 14     |            _ |           - |            - |
| 0      |            _ |           - |          Set |
| 0      |            _ |           - |        Reset |
| 0      |            _ |         Set |            - |
| 0      |            _ |       Reset |            - |
| 0      |          Yes |           - |            - |
| 7028   |          Yes |           - |          Set |
| 42158  |          Yes |           - |        Reset |
| 3838   |          Yes |         Set |            - |
| 269033 |          Yes |       Reset |            - |
+--------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+--------------------------------------------+--------+-----------+-------+
|                  Site Type                 |  Used  | Available | Util% |
+--------------------------------------------+--------+-----------+-------+
| Slice                                      |  68375 |     69350 | 98.59 |
|   SLICEL                                   |  41675 |           |       |
|   SLICEM                                   |  26700 |           |       |
| LUT as Logic                               | 163406 |    277400 | 58.91 |
|   using O5 output only                     |     56 |           |       |
|   using O6 output only                     | 120070 |           |       |
|   using O5 and O6                          |  43280 |           |       |
| LUT as Memory                              |  30265 |    108200 | 27.97 |
|   LUT as Distributed RAM                   |  11018 |           |       |
|     using O5 output only                   |      0 |           |       |
|     using O6 output only                   |    462 |           |       |
|     using O5 and O6                        |  10556 |           |       |
|   LUT as Shift Register                    |  19247 |           |       |
|     using O5 output only                   |   8803 |           |       |
|     using O6 output only                   |   6174 |           |       |
|     using O5 and O6                        |   4270 |           |       |
| Slice Registers                            | 322013 |    554800 | 58.04 |
|   Register driven from within the Slice    | 161137 |           |       |
|   Register driven from outside the Slice   | 160876 |           |       |
|     LUT in front of the register is unused |  93353 |           |       |
|     LUT in front of the register is used   |  67523 |           |       |
| Unique Control Sets                        |  10305 |     69350 | 14.86 |
+--------------------------------------------+--------+-----------+-------+
* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.


3. Memory
---------

+-------------------+------+-----------+-------+
|     Site Type     | Used | Available | Util% |
+-------------------+------+-----------+-------+
| Block RAM Tile    |  596 |       755 | 78.94 |
|   RAMB36/FIFO*    |  516 |       755 | 68.34 |
|     RAMB36E1 only |  516 |           |       |
|   RAMB18          |  160 |      1510 | 10.60 |
|     RAMB18E1 only |  160 |           |       |
+-------------------+------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-----------+-------+
|    Site Type   | Used | Available | Util% |
+----------------+------+-----------+-------+
| DSPs           |  612 |      2020 | 30.30 |
|   DSP48E1 only |  612 |           |       |
+----------------+------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-----------+--------+
|          Site Type          | Used | Available |  Util% |
+-----------------------------+------+-----------+--------+
| Bonded IOB                  |  253 |       362 |  69.89 |
|   IOB Master Pads           |  129 |           |        |
|   IOB Slave Pads            |  124 |           |        |
|   IOB Flip Flops            |   58 |           |        |
| Bonded IPADs                |   28 |        50 |  56.00 |
| Bonded OPADs                |   20 |        32 |  62.50 |
| Bonded IOPADs               |  130 |       130 | 100.00 |
| PHY_CONTROL                 |    2 |         8 |  25.00 |
| PHASER_REF                  |    2 |         8 |  25.00 |
| OUT_FIFO                    |    8 |        32 |  25.00 |
| IN_FIFO                     |    4 |        32 |  12.50 |
| IDELAYCTRL                  |    1 |         8 |  12.50 |
| IBUFDS                      |    8 |       348 |   2.30 |
| GTXE2_COMMON                |    3 |         4 |  75.00 |
| GTXE2_CHANNEL               |   10 |        16 |  62.50 |
| PHASER_OUT/PHASER_OUT_PHY   |    8 |        32 |  25.00 |
|   PHASER_OUT_PHY only       |    8 |           |        |
| PHASER_IN/PHASER_IN_PHY     |    4 |        32 |  12.50 |
|   PHASER_IN_PHY only        |    4 |           |        |
| IDELAYE2/IDELAYE2_FINEDELAY |   32 |       400 |   8.00 |
|   IDELAYE2 only             |   32 |           |        |
| ODELAYE2/ODELAYE2_FINEDELAY |    0 |       150 |   0.00 |
| IBUFDS_GTE2                 |    4 |         8 |  50.00 |
| ILOGIC                      |   40 |       362 |  11.05 |
|   IFF_IDDR_Register         |    8 |           |        |
|   ISERDES                   |   32 |       362 |        |
| OLOGIC                      |  132 |       362 |  36.46 |
|   OUTFF_Register            |   58 |           |        |
|   OUTFF_ODDR_Register       |    9 |           |        |
|   TFF_ODDR_Register         |    4 |           |        |
|   OSERDES                   |   65 |       362 |        |
+-----------------------------+------+-----------+--------+


6. Clocking
-----------

+------------+------+-----------+-------+
|  Site Type | Used | Available | Util% |
+------------+------+-----------+-------+
| BUFGCTRL   |   16 |        32 | 50.00 |
| BUFIO      |    0 |        32 |  0.00 |
| MMCME2_ADV |    4 |         8 | 50.00 |
| PLLE2_ADV  |    1 |         8 | 12.50 |
| BUFMRCE    |    0 |        16 |  0.00 |
| BUFHCE     |    7 |       168 |  4.17 |
| BUFR       |    1 |        32 |  3.13 |
+------------+------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-----------+--------+
|  Site Type  | Used | Available |  Util% |
+-------------+------+-----------+--------+
| BSCANE2     |    0 |         4 |   0.00 |
| CAPTUREE2   |    0 |         1 |   0.00 |
| DNA_PORT    |    0 |         1 |   0.00 |
| EFUSE_USR   |    0 |         1 |   0.00 |
| FRAME_ECCE2 |    0 |         1 |   0.00 |
| ICAPE2      |    0 |         2 |   0.00 |
| PCIE_2_1    |    0 |         1 |   0.00 |
| STARTUPE2   |    0 |         1 |   0.00 |
| XADC        |    1 |         1 | 100.00 |
+-------------+------+-----------+--------+


8. Primitives
-------------

+------------------------+--------+----------------------+
|        Ref Name        |  Used  |  Functional Category |
+------------------------+--------+----------------------+
| FDRE                   | 269033 |         Flop & Latch |
| LUT3                   |  63712 |                  LUT |
| LUT6                   |  47623 |                  LUT |
| FDCE                   |  42158 |         Flop & Latch |
| LUT2                   |  34263 |                  LUT |
| LUT5                   |  28165 |                  LUT |
| LUT4                   |  27169 |                  LUT |
| SRL16E                 |  17934 |   Distributed Memory |
| RAMD32                 |  16630 |   Distributed Memory |
| CARRY4                 |  13998 |           CarryLogic |
| FDPE                   |   7028 |         Flop & Latch |
| LUT1                   |   5754 |                  LUT |
| SRLC32E                |   5583 |   Distributed Memory |
| MUXF7                  |   4779 |                MuxFx |
| RAMS32                 |   4624 |   Distributed Memory |
| FDSE                   |   3838 |         Flop & Latch |
| MUXF8                  |   1798 |                MuxFx |
| DSP48E1                |    612 |     Block Arithmetic |
| RAMB36E1               |    516 |         Block Memory |
| RAMS64E                |    192 |   Distributed Memory |
| OBUF                   |    172 |                   IO |
| RAMB18E1               |    160 |         Block Memory |
| BIBUF                  |    130 |                   IO |
| RAMD64E                |    128 |   Distributed Memory |
| OSERDESE2              |     65 |                   IO |
| IBUF                   |     61 |                   IO |
| OBUFT_DCIEN            |     32 |                   IO |
| ISERDESE2              |     32 |                   IO |
| IDELAYE2               |     32 |                   IO |
| IBUF_IBUFDISABLE       |     32 |                   IO |
| OBUFT                  |     26 |                   IO |
| ODDR                   |     13 |                   IO |
| AND2B1L                |     12 |               Others |
| BUFG                   |     11 |                Clock |
| GTXE2_CHANNEL          |     10 |                   IO |
| PHASER_OUT_PHY         |      8 |                   IO |
| OUT_FIFO               |      8 |                   IO |
| OBUFTDS_DCIEN          |      8 |                   IO |
| IDDR                   |      8 |                   IO |
| IBUFDS_IBUFDISABLE_INT |      8 |                   IO |
| IBUFDS                 |      8 |                   IO |
| INV                    |      5 |                  LUT |
| BUFH                   |      5 |                Clock |
| BUFGCTRL               |      5 |                Clock |
| PHASER_IN_PHY          |      4 |                   IO |
| MMCME2_ADV             |      4 |                Clock |
| IN_FIFO                |      4 |                   IO |
| IBUFDS_GTE2            |      4 |                   IO |
| GTXE2_COMMON           |      3 |                   IO |
| PHY_CONTROL            |      2 |                   IO |
| PHASER_REF             |      2 |                   IO |
| OR2L                   |      2 |               Others |
| OBUFDS                 |      2 |                   IO |
| BUFHCE                 |      2 |                Clock |
| XADC                   |      1 |               Others |
| USR_ACCESSE2           |      1 |               Others |
| PS7                    |      1 | Specialized Resource |
| PLLE2_ADV              |      1 |                Clock |
| IDELAYCTRL             |      1 |                   IO |
| BUFR                   |      1 |                Clock |
+------------------------+--------+----------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+------------------------+------+
|        Ref Name        | Used |
+------------------------+------+
| fifo_short_2clk        |  216 |
| fifo_4k_2clk           |   48 |
| dds_sin_cos_lut_only   |    8 |
| complex_multiplier_dds |    8 |
| axi_hb47               |    8 |
| axi_fft                |    6 |
| hbdec3                 |    4 |
| hbdec2                 |    4 |
| hbdec1                 |    4 |
| complex_multiplier     |    4 |
| axi64_4k_2clk_fifo     |    4 |
| TdcCore                |    4 |
| ten_gig_eth_pcs_pma    |    2 |
| axi_eth_dma            |    2 |
| SyncRegsIfc            |    2 |
| Jesd204bXcvrCore       |    2 |
| misc_clock_gen         |    1 |
| ddr3_32bit             |    1 |
+------------------------+------+


Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3_AR71898 (lin64) Build 2405991 Thu Dec  6 23:36:41 MST 2018
| Date         : Fri Jan 31 14:21:18 2020
| Host         : pratthpc.crc.nd.edu running 64-bit Red Hat Enterprise Linux Server release 7.7 (Maipo)
| Command      : report_timing_summary -no_detailed_paths -file /afs/crc.nd.edu/user/r/rkossler/uhd/UHD-3.15.0.0/uhd/fpga-src/usrp3/top/n3xx/build-N310_RFNOC_XG/build.rpt -append
| Design       : n3xx
| Device       : 7z100-ffg900
| Speed File   : -2  PRODUCTION 1.11 2014-09-11
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There is 1 register/latch pin which need pulse_width check. (LOW)


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 3 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)


5. checking no_input_delay
--------------------------
 There are 6 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 7 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 2 ports with no output delay but with a timing clock defined on it or propagating through it (LOW)


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.010        0.000                      0               963889        0.047        0.000                      0               963441        0.001        0.000                       0                369569  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                                                                            Waveform(ns)         Period(ns)      Frequency(MHz)
-----                                                                                                                                                            ------------         ----------      --------------
async_in_clk                                                                                                                                                     {0.000 25.000}       50.000          20.000          
async_out_clk                                                                                                                                                    {0.000 25.000}       50.000          20.000          
bus_clk                                                                                                                                                          {0.000 2.500}        5.000           200.000         
clk100                                                                                                                                                           {0.000 5.000}        10.000          100.000         
clk40                                                                                                                                                            {0.000 12.500}       25.000          40.000          
ddr3_ext_refclk                                                                                                                                                  {0.000 5.000}        10.000          100.000         
  freq_refclk_1                                                                                                                                                  {1.442 2.212}        1.538           650.000         
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk_1  {1.442 2.212}        1.538           650.000         
      iserdes_clkdiv_4                                                                                                                                           {1.442 2.981}        3.077           325.000         
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk_1  {1.442 2.212}        1.538           650.000         
      iserdes_clkdiv_5                                                                                                                                           {1.442 2.981}        3.077           325.000         
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk_1  {1.442 2.212}        1.538           650.000         
      iserdes_clkdiv_6                                                                                                                                           {1.442 2.981}        3.077           325.000         
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk_1  {1.442 2.212}        1.538           650.000         
      iserdes_clkdiv_7                                                                                                                                           {1.442 2.981}        3.077           325.000         
  mem_refclk_1                                                                                                                                                   {0.000 0.769}        1.538           650.000         
    oserdes_clk_10                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_10                                                                                                                                          {0.000 1.538}        3.077           325.000         
    oserdes_clk_11                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_11                                                                                                                                          {0.000 1.538}        3.077           325.000         
    oserdes_clk_12                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_12                                                                                                                                          {0.000 3.077}        6.154           162.500         
    oserdes_clk_13                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_13                                                                                                                                          {0.000 3.077}        6.154           162.500         
    oserdes_clk_14                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_14                                                                                                                                          {0.000 3.077}        6.154           162.500         
    oserdes_clk_15                                                                                                                                               {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_15                                                                                                                                          {0.000 3.077}        6.154           162.500         
    oserdes_clk_8                                                                                                                                                {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_8                                                                                                                                           {0.000 1.538}        3.077           325.000         
    oserdes_clk_9                                                                                                                                                {0.000 0.769}        1.538           650.000         
      oserdes_clkdiv_9                                                                                                                                           {0.000 1.538}        3.077           325.000         
  pll_clk3_out_1                                                                                                                                                 {0.000 3.077}        6.154           162.500         
    ddr3_ui_clk                                                                                                                                                  {0.000 3.077}        6.154           162.500         
    ddr3_ui_clk_2x                                                                                                                                               {0.000 6.154}        12.308          81.250          
  pll_clkfbout_1                                                                                                                                                 {0.000 5.000}        10.000          100.000         
  sync_pulse_1                                                                                                                                                   {0.673 2.212}        24.615          40.625          
fpga_clk_a                                                                                                                                                       {0.000 3.255}        6.510           153.610         
  radio_clk                                                                                                                                                      {0.000 3.255}        6.510           153.610         
    atr_bus_clk                                                                                                                                                  {0.000 6.510}        13.020          76.805          
    dsa_bus_clk                                                                                                                                                  {0.000 6.510}        13.020          76.805          
    fp_gpio_bus_clk                                                                                                                                              {0.000 6.510}        13.020          76.805          
    pl_spi_clk_a                                                                                                                                                 {0.000 162.750}      325.500         3.072           
    pl_spi_clk_b                                                                                                                                                 {0.000 162.750}      325.500         3.072           
  radio_clk_fb                                                                                                                                                   {0.000 3.255}        6.510           153.610         
fpga_clk_a_v                                                                                                                                                     {0.000 3.255}        6.510           153.610         
fpga_clk_b                                                                                                                                                       {0.000 3.255}        6.510           153.610         
  radio_clk_b                                                                                                                                                    {0.000 3.255}        6.510           153.610         
  radio_clk_b_fb                                                                                                                                                 {0.000 3.255}        6.510           153.610         
fpga_clk_b_v                                                                                                                                                     {0.000 3.255}        6.510           153.610         
ge_phy_clk                                                                                                                                                       {0.000 4.000}        8.000           125.000         
meas_clk_ref                                                                                                                                                     {0.000 3.000}        6.000           166.667         
  ddr3_dma_clk_misc_clock_gen                                                                                                                                    {0.000 1.646}        3.291           303.819         
  meas_clk                                                                                                                                                       {0.000 2.520}        5.040           198.413         
  meas_clk_fb                                                                                                                                                    {0.000 9.000}        18.000          55.556          
mgt_clk_dba                                                                                                                                                      {0.000 3.255}        6.510           153.610         
mgt_clk_dbb                                                                                                                                                      {0.000 3.255}        6.510           153.610         
net_clk                                                                                                                                                          {0.000 4.000}        8.000           125.000         
ref_clk                                                                                                                                                          {0.000 20.000}       40.000          25.000          
sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/RXOUTCLK       {0.000 1.551}        3.103           322.269         
sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK       {0.000 1.551}        3.103           322.269         
sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/RXOUTCLK       {0.000 1.551}        3.103           322.269         
sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK       {0.000 1.551}        3.103           322.269         
xge_clk                                                                                                                                                          {0.000 3.200}        6.400           156.250         
  dclk_buf                                                                                                                                                       {0.000 6.400}        12.800          78.125          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                                                                                WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                                                                                -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
bus_clk                                                                                                                                                                0.016        0.000                      0               240813        0.047        0.000                      0               240813        0.264        0.000                       0                101139  
clk40                                                                                                                                                                  6.950        0.000                      0                85857        0.052        0.000                      0                85497       11.500        0.000                       0                 35533  
ddr3_ext_refclk                                                                                                                                                                                                                                                                                                    3.000        0.000                       0                     1  
  freq_refclk_1                                                                                                                                                                                                                                                                                                    0.287        0.000                       0                    15  
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk_1                                                                                                                                                    0.468        0.000                       0                    16  
      iserdes_clkdiv_4                                                                                                                                                 1.555        0.000                      0                   33        0.070        0.000                      0                   33        0.624        0.000                       0                     9  
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk_1                                                                                                                                                    0.468        0.000                       0                    16  
      iserdes_clkdiv_5                                                                                                                                                 1.569        0.000                      0                   33        0.070        0.000                      0                   33        0.624        0.000                       0                     9  
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk_1                                                                                                                                                    0.468        0.000                       0                    16  
      iserdes_clkdiv_6                                                                                                                                                 1.574        0.000                      0                   33        0.070        0.000                      0                   33        0.624        0.000                       0                     9  
    u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk_1                                                                                                                                                    0.468        0.000                       0                    16  
      iserdes_clkdiv_7                                                                                                                                                 1.550        0.000                      0                   33        0.070        0.000                      0                   33        0.624        0.000                       0                     9  
  mem_refclk_1                                                                                                                                                         0.461        0.000                      0                    2        0.324        0.000                      0                    2        0.234        0.000                       0                    15  
    oserdes_clk_10                                                                                                                                                     0.474        0.000                      0                    4        0.371        0.000                      0                    4        0.468        0.000                       0                    12  
      oserdes_clkdiv_10                                                                                                                                                1.791        0.000                      0                   36        0.066        0.000                      0                   36        0.624        0.000                       0                    11  
    oserdes_clk_11                                                                                                                                                     0.486        0.000                      0                    4        0.364        0.000                      0                    4        0.468        0.000                       0                    12  
      oserdes_clkdiv_11                                                                                                                                                1.895        0.000                      0                   36        0.062        0.000                      0                   36        0.624        0.000                       0                    11  
    oserdes_clk_12                                                                                                                                                                                                                                                                                                 0.468        0.000                       0                     1  
      oserdes_clkdiv_12                                                                                                                                                5.169        0.000                      0                    4        0.072        0.000                      0                    4        2.163        0.000                       0                     2  
    oserdes_clk_13                                                                                                                                                                                                                                                                                                 0.468        0.000                       0                     8  
      oserdes_clkdiv_13                                                                                                                                                5.159        0.000                      0                   28        0.072        0.000                      0                   28        2.163        0.000                       0                     8  
    oserdes_clk_14                                                                                                                                                                                                                                                                                                 0.468        0.000                       0                     7  
      oserdes_clkdiv_14                                                                                                                                                5.160        0.000                      0                   28        0.070        0.000                      0                   28        2.163        0.000                       0                     8  
    oserdes_clk_15                                                                                                                                                                                                                                                                                                 0.468        0.000                       0                    10  
      oserdes_clkdiv_15                                                                                                                                                4.972        0.000                      0                   40        0.062        0.000                      0                   40        2.163        0.000                       0                    11  
    oserdes_clk_8                                                                                                                                                      0.479        0.000                      0                    4        0.369        0.000                      0                    4        0.468        0.000                       0                    12  
      oserdes_clkdiv_8                                                                                                                                                 2.092        0.000                      0                   36        0.064        0.000                      0                   36        0.624        0.000                       0                    11  
    oserdes_clk_9                                                                                                                                                      0.466        0.000                      0                    4        0.375        0.000                      0                    4        0.468        0.000                       0                    12  
      oserdes_clkdiv_9                                                                                                                                                 2.082        0.000                      0                   36        0.068        0.000                      0                   36        0.624        0.000                       0                    11  
  pll_clk3_out_1                                                                                                                                                                                                                                                                                                   1.577        0.000                       0                     3  
    ddr3_ui_clk                                                                                                                                                        0.215        0.000                      0                51173        0.051        0.000                      0                51173        1.827        0.000                       0                 21281  
    ddr3_ui_clk_2x                                                                                                                                                     3.729        0.000                      0                   16        0.119        0.000                      0                   16        5.754        0.000                       0                    20  
  pll_clkfbout_1                                                                                                                                                                                                                                                                                                   8.929        0.000                       0                     2  
  sync_pulse_1                                                                                                                                                                                                                                                                                                     0.466        0.000                       0                    15  
fpga_clk_a                                                                                                                                                                                                                                                                                                         1.755        0.000                       0                     1  
  radio_clk                                                                                                                                                            0.120        0.000                      0               477023        0.050        0.000                      0               477023        2.487        0.000                       0                182898  
  radio_clk_fb                                                                                                                                                                                                                                                                                                     5.102        0.000                       0                     3  
fpga_clk_b                                                                                                                                                                                                                                                                                                         1.755        0.000                       0                     1  
  radio_clk_b                                                                                                                                                          2.611        0.000                      0                  202        0.108        0.000                      0                  202        2.855        0.000                       0                   147  
  radio_clk_b_fb                                                                                                                                                                                                                                                                                                   5.102        0.000                       0                     3  
meas_clk_ref                                                                                                                                                                                                                                                                                                       1.500        0.000                       0                     2  
  ddr3_dma_clk_misc_clock_gen                                                                                                                                          0.010        0.000                      0                42401        0.053        0.000                      0                42401        0.878        0.000                       0                 15257  
  meas_clk                                                                                                                                                             0.710        0.000                      0                 3418        0.053        0.000                      0                 3418        2.120        0.000                       0                  1813  
  meas_clk_fb                                                                                                                                                                                                                                                                                                     16.929        0.000                       0                     2  
mgt_clk_dba                                                                                                                                                            5.716        0.000                      0                    1        0.321        0.000                      0                    1        2.855        0.000                       0                     9  
mgt_clk_dbb                                                                                                                                                            6.077        0.000                      0                    1        0.149        0.000                      0                    1        2.855        0.000                       0                     9  
net_clk                                                                                                                                                                                                                                                                                                            6.592        0.000                       0                     1  
ref_clk                                                                                                                                                                1.473        0.000                      0                 1090        0.108        0.000                      0                 1090       19.600        0.000                       0                   797  
sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/RXOUTCLK             0.029        0.000                      0                 3774        0.055        0.000                      0                 3774        0.001        0.000                       0                  1464  
sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK             0.755        0.000                      0                  339        0.085        0.000                      0                  339        0.001        0.000                       0                   203  
sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/RXOUTCLK             0.218        0.000                      0                 3774        0.058        0.000                      0                 3774        0.001        0.000                       0                  1464  
sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK             0.924        0.000                      0                  339        0.108        0.000                      0                  339        0.001        0.000                       0                   203  
xge_clk                                                                                                                                                                0.719        0.000                      0                13028        0.055        0.000                      0                13026        2.432        0.000                       0                  6776  
  dclk_buf                                                                                                                                                            10.034        0.000                      0                  370        0.108        0.000                      0                  370        6.000        0.000                       0                   245  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                                                                                   To Clock                                                                                                                                                         WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                                                                                   --------                                                                                                                                                         -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
                                                                                                                                                             async_out_clk                                                                                                                                                     40.443        0.000                      0                    4        3.283        0.000                      0                    4  
bus_clk                                                                                                                                                      async_out_clk                                                                                                                                                     36.033        0.000                      0                    5        3.266        0.000                      0                    5  
clk40                                                                                                                                                        async_out_clk                                                                                                                                                     39.861        0.000                      0                    2        5.070        0.000                      0                    2  
radio_clk                                                                                                                                                    async_out_clk                                                                                                                                                     43.889        0.000                      0                    7        1.007        0.000                      0                    7  
atr_bus_clk                                                                                                                                                  async_out_clk                                                                                                                                                     47.944        0.000                      0                    1        1.406        0.000                      0                    1  
dsa_bus_clk                                                                                                                                                  async_out_clk                                                                                                                                                     47.914        0.000                      0                    1        1.436        0.000                      0                    1  
fp_gpio_bus_clk                                                                                                                                              async_out_clk                                                                                                                                                     44.023        0.000                      0                    1        4.614        0.000                      0                    1  
radio_clk_b                                                                                                                                                  async_out_clk                                                                                                                                                     47.969        0.000                      0                    1        0.335        0.000                      0                    1  
ref_clk                                                                                                                                                      async_out_clk                                                                                                                                                     41.943        0.000                      0                    2        3.702        0.000                      0                    2  
sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK   async_out_clk                                                                                                                                                     35.803        0.000                      0                    1        7.890        0.000                      0                    1  
sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK   async_out_clk                                                                                                                                                     35.443        0.000                      0                    1        8.059        0.000                      0                    1  
ddr3_ui_clk                                                                                                                                                  u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk_1        4.293        0.000                      0                    8       23.401        0.000                      0                    8  
ddr3_ui_clk                                                                                                                                                  u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk_1        3.575        0.000                      0                    8       23.974        0.000                      0                    8  
ddr3_ui_clk                                                                                                                                                  u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk_1        2.832        0.000                      0                    8       24.422        0.000                      0                    8  
ddr3_ui_clk                                                                                                                                                  u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk_1        1.770        0.000                      0                    8       24.888        0.000                      0                    8  
sync_pulse_1                                                                                                                                                 mem_refclk_1                                                                                                                                                       0.375        0.000                      0                    2        0.200        0.000                      0                    2  
oserdes_clk_10                                                                                                                                               oserdes_clkdiv_10                                                                                                                                                  0.722        0.000                      0                   15        0.075        0.000                      0                   15  
oserdes_clk_11                                                                                                                                               oserdes_clkdiv_11                                                                                                                                                  0.432        0.000                      0                   15        0.094        0.000                      0                   15  
oserdes_clk_12                                                                                                                                               oserdes_clkdiv_12                                                                                                                                                  0.789        0.000                      0                    2        0.094        0.000                      0                    2  
oserdes_clk_13                                                                                                                                               oserdes_clkdiv_13                                                                                                                                                  0.789        0.000                      0                    8        0.078        0.000                      0                    8  
oserdes_clk_14                                                                                                                                               oserdes_clkdiv_14                                                                                                                                                  0.772        0.000                      0                    8        0.094        0.000                      0                    8  
oserdes_clk_15                                                                                                                                               oserdes_clkdiv_15                                                                                                                                                  0.473        0.000                      0                   11        0.094        0.000                      0                   11  
oserdes_clk_8                                                                                                                                                oserdes_clkdiv_8                                                                                                                                                   0.789        0.000                      0                   15        0.073        0.000                      0                   15  
oserdes_clk_9                                                                                                                                                oserdes_clkdiv_9                                                                                                                                                   0.715        0.000                      0                   15        0.077        0.000                      0                   15  
ddr3_ui_clk_2x                                                                                                                                               ddr3_ui_clk                                                                                                                                                        3.623        0.000                      0                    5        0.098        0.000                      0                    5  
ddr3_ui_clk                                                                                                                                                  ddr3_ui_clk_2x                                                                                                                                                     0.863        0.000                      0                    1        2.059        0.000                      0                    1  
fp_gpio_bus_clk                                                                                                                                              radio_clk                                                                                                                                                         37.969        0.000                      0                    1        6.389        0.000                      0                    1  
pl_spi_clk_a                                                                                                                                                 radio_clk                                                                                                                                                         84.674        0.000                      0                    1       17.731        0.000                      0                    1  
pl_spi_clk_b                                                                                                                                                 radio_clk                                                                                                                                                         84.129        0.000                      0                    1       18.030        0.000                      0                    1  
fpga_clk_a_v                                                                                                                                                 radio_clk                                                                                                                                                          1.024        0.000                      0                    1        1.056        0.000                      0                    1  
radio_clk_b                                                                                                                                                  radio_clk                                                                                                                                                          3.922        0.000                      0                    1        0.600        0.000                      0                    1  
radio_clk                                                                                                                                                    atr_bus_clk                                                                                                                                                        1.366        0.000                      0                    7        0.361        0.000                      0                    7  
radio_clk                                                                                                                                                    dsa_bus_clk                                                                                                                                                        0.290        0.000                      0                   47        0.261        0.000                      0                   47  
radio_clk                                                                                                                                                    fp_gpio_bus_clk                                                                                                                                                    3.289        0.000                      0                   11        0.177        0.000                      0                   11  
radio_clk                                                                                                                                                    pl_spi_clk_a                                                                                                                                                       7.926        0.000                      0                    4        8.474        0.000                      0                    4  
radio_clk                                                                                                                                                    pl_spi_clk_b                                                                                                                                                       8.327        0.000                      0                    4        8.060        0.000                      0                    4  
radio_clk                                                                                                                                                    fpga_clk_a_v                                                                                                                                                       0.260        0.000                      0                    1        0.565        0.000                      0                    1  
fpga_clk_b_v                                                                                                                                                 radio_clk_b                                                                                                                                                        1.431        0.000                      0                    1        0.765        0.000                      0                    1  
dclk_buf                                                                                                                                                     xge_clk                                                                                                                                                            2.333        0.000                      0                   32                                                                        
xge_clk                                                                                                                                                      dclk_buf                                                                                                                                                           2.007        0.000                      0                   52                                                                        


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                                                                                  From Clock                                                                                                                                                  To Clock                                                                                                                                                        WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                                                                                  ----------                                                                                                                                                  --------                                                                                                                                                        -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                                                                           bus_clk                                                                                                                                                     bus_clk                                                                                                                                                           0.092        0.000                      0                19930        0.140        0.000                      0                19930  
**async_default**                                                                                                                                           clk40                                                                                                                                                       clk40                                                                                                                                                            10.157        0.000                      0                 4547        0.205        0.000                      0                 4547  
**async_default**                                                                                                                                           ddr3_dma_clk_misc_clock_gen                                                                                                                                 ddr3_dma_clk_misc_clock_gen                                                                                                                                       0.139        0.000                      0                 1639        0.161        0.000                      0                 1639  
**async_default**                                                                                                                                           ddr3_ui_clk                                                                                                                                                 ddr3_ui_clk                                                                                                                                                       0.651        0.000                      0                  499        0.159        0.000                      0                  499  
**async_default**                                                                                                                                           radio_clk                                                                                                                                                   radio_clk                                                                                                                                                         1.380        0.000                      0                10836        0.114        0.000                      0                10836  
**async_default**                                                                                                                                           sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK  sfp_wrapper_0/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK        2.304        0.000                      0                    1        0.295        0.000                      0                    1  
**async_default**                                                                                                                                           sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK  sfp_wrapper_1/lanes[0].lane_i/mgt_io_i/ten_gige_phy_i/ten_gig_eth_pcs_pma_i/inst/gt0_gtwizard_10gbaser_multi_gt_i/gt0_gtwizard_10gbaser_i/gtxe2_i/TXOUTCLK        2.226        0.000                      0                    1        0.325        0.000                      0                    1  
**async_default**                                                                                                                                           xge_clk                                                                                                                                                     xge_clk                                                                                                                                                           0.574        0.000                      0                 2090        0.729        0.000                      0                 2090  
**default**                                                                                                                                                                                                                                                                                                                                                                                                                                                                               1.533        0.000                      0                   18        1.000        0.000                      0                   18  
**default**                                                                                                                                                 ddr3_ui_clk                                                                                                                                                                                                                                                                                                                   0.430        0.000                      0                    2                                                                        
**default**                                                                                                                                                 input port clock                                                                                                                                                                                                                                                                                                              1.487        0.000                      0                    2        1.453        0.000                      0                    2  


