Hi everybody, we are using an external 10MHz clock for the B200mini and have some concerns/questions about the clocking architecture:
1. Do I see it correctly from the schematics, that the external 10MHz reference is used in a control-loop within the FPGA to actually steer the 40MHz VCTCXO with the DAC? 2. We used two B200mini with the same external clock and saw some weird bumps in the Allan deviation plot, indicating partly contributions from a whatsoever control loop and from the VCTCXO. 3. Why has the B200mini clocking architecture been chosen like that? a. Is the same architecture used for the B210 as well? 4. How is the control loop for the external clock exactly implemented, and which parameters are used? a. Are stability characteristics of the used VCTCXO taken into account? b. Could those parameters bee changed? If so, where and how? Best regards, Emanuel
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