Hello, We are trying to integrate a custom module into RFNOC from Xilinx System Generator. Has anyone determined the best design flow for this process?
We have exported a simple SysGen design (based on a digital gain block) as a synthesized checkpoint, but have been unable to connect the design into the vivado project used by the uhd_image_builder.py script. To create the Vivado project we executed the uhd_image_builder.py script with commands from the RFNOC Getting Started tutorial, cancelled the bitstream generation, and saved the project. We cancelled the bitstream generation because the script would cause the generation to run to completion (including Vivado exiting) and we would be unable to save the project. Ultimately we would like to repeat the design process for larger SysGen models, so we would like to determine the process without converting the model to Verilog and following the RFNOC OOT Module method. Thank you for your help. Marko
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