On Thu, Dec 1, 2011 at 12:29, Casper Wandahl Schmidt <kalle.pri...@gmail.com> wrote: [...] > > That didn't quite help me understand, because how can the OS map from ie. > 0-4GB to 4-8GB (the window is moved) when it can only use a 32bit register > to tell the machine where to look in the psysical memory, that is where my > knowledge ends :) So I read about PAE and found out that it uses 2 registers > (36 bits due to some bits being used as flags) and that makes good sense, > but how can the cpu calculate an address without overflow and send a command > to the bus containing a 36bit address (or whatever fetches the bits from > RAM)? That is where I'm puzzled but I guess it is because I'm not at all > into ISA-level and below :) >
It is the role of the MMU to do that. At any one time, it can map a "virtual", 32-bit wide, address to a "real", 36-bit wide address. It uses TLBs (Translation Lookaside Buffers) for that, and it is the OS' role to have the correct TLB in place at any time. -- Francis Galiegue ONE2TEAM Ingénieur système Mob : +33 (0) 683 877 875 Tel : +33 (0) 178 945 552 f...@one2team.com 40 avenue Raymond Poincaré 75116 Paris --------------------------------------------------------------------- To unsubscribe, e-mail: users-unsubscr...@tomcat.apache.org For additional commands, e-mail: users-h...@tomcat.apache.org
