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*************************************************** GIM2P Special Session 2015 Special Session on General Issues in Many-core Programming & Programmability https://sites.google.com/site/gim2psession/ IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2015) http://mcsoc-forum.org/ Turin, Italy, 23-25 September 2015 *************************************************** The IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip aims at providing the world’s premier forum of leading researchers in the embedded Multicore/Many-core SoCs software, tools and applications design areas for Academia and industries. Prospective authors are invited to submit paper of their works.Submission of a paper implies that at least one of the authors will have a full registration to the symposium upon acceptance of the paper. The Symposium will be held in TURIN, Italy. The city of the 2006 Olympic Games! Important Dates *************** Paper Submission: March 31, 2015 Notification of Acceptance: June 22, 2014 Camera Ready Paper: June 30, 2015 Symposium Date: September 23-25, 2015 Call for papers *************** As an emerging trend in microprocessor architecture and as single-core processors' performance reached a plateau by hitting the so-called power (or heat) wall, new designs focus on augmenting the number of cores in a single processor to increase performance without increasing power consumption. This has now lead to a new category of microprocessors with several dozens computing cores on a single chip, which are usually known as many-core processors. Several example are already available: Intel Xeon Phi (57 cores), Tilera GX (63 cores), Kalray MPPA-256 (256 cores), ST Micro STHORM, and even the crowd-funded 64-core Parallella Epiphany chip. The trend is expected to continue with future many-core systems with hundreds, and may be thousands of cores. But as these processors emerge, the real issue about utilizing them and obtaining the targeted performance is the programming and programmability challenge: To harness this kind of computing power, an efficient way of doing parallel programming is required. Such a level of parallel programming is knowledgeably difficult to design to, and to manage. Therefore, this problem is a major research opportunity and a major challenge for the future of programming. Special Session Scope ********************* This session addresses all aspects of many-core systems programming, the issues encountered as programming existing one, and new approaches toward minimizing them. For the latter, it can range in all aspects from new programming languages or high-level software approaches to new hardware features designed to help the life of the programmer, of the compilation tools or the execution support. Authors are invited to submit high quality papers representing original work from both the academia and industry in the following topics (but not limited to them). Topics ****** Topics include, but are not limited to: * Programming models and languages for many-cores * Compilers for programming languages * Runtime generation for parallel programming on manycores * Architecture support for massive parallelism management * Enhanced communications for CMP/manycores * Shared memory, data consistency models and protocols * New operating systems, or dedicated OS * Security, crypto systems for manycores * User feedback on existing manycore architectures (experiments with Adapteva Epiphany, Intel Phi, Kalray MPPA, ST STHorm, Tilera Gx, TSAR..etc) Proceedings Publication and Indexing ************************************ MCSoC-15 proceedings will be published by IEEE CS Press, which will be included in the Computer Society Digital Library CSDL and IEEE Xplore. All CPS conference publications are also submitted for indexing to EI’s Engineering Information Index, Compendex, and ISI Thomson’s Scientific and Technical Proceedings, ISTP/ISI Proceedings, and ISI Thomson. Program Committee ***************** (to be extended) Camille COTI, Université de Paris-Nord, France Loïc CUDENNEC, CEA, LIST, France Aleksandar DRAGOJEVIC, Microsoft Research Cambridge, UK Sven KAROL, TU Dresden, Germany Vianney LAPOTRE, Université de Bretagne-Sud, France Stéphane LOUISE, CEA, LIST, France Marco MATTAVELLI, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland Maximilian ODENDAHL, Silexica / RWTH Aachen University, Germany Eric PETIT, Université de Versailles Saint Quentin-en-Yvelines, France Mickaël RAULET, ATEME Rennes, France Jason RIEDY, Georgia Institute of Technology, USA Martha Johanna SEPULVEDA, INRIA, École Centrale de Lyon, France -- Loïc CUDENNEC http://www.cudennec.fr/ CEA, LIST, Nano-INNOV / Saclay PC 172, 91191 Gif-sur-Yvette CEDEX +33 1 69 08 00 58
