commit f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36
Author: Ville Syrjälä <ville.syrj...@linux.intel.com>
Date: Tue Feb 11 19:52:06 2014 +0200
drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.
v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)
Cc: Bjoern C <l...@call-home.ch>
Cc: Alexandru DAMIAN <alexandru.dam...@intel.com>
Cc: Enrico Tagliavini <enrico.tagliav...@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: sta...@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
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https://bugs.launchpad.net/bugs/1274779
Title:
[ivb] hang on pageflip (IPEHR: 0x0a000001 or 0x0a080001 depending on
pipe)
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