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On 2012-02-17T09:57:34+00:00 Bernhard Rosenkraenzer wrote:

Created attachment 26693
Preprocessed source triggering this issue

[bero@localhost ~]$ /opt/android-toolchain-4.7/bin/arm-linux-androideabi-g++ 
-mcpu=cortex-a9 -mthumb -Os -o agc2_amr_wb.o -c agc2_amr_wb.i 
/tmp/ccBg0Qr8.s: Assembler messages:
/tmp/ccBg0Qr8.s:110: Error: branch out of range

The problem disappears when taking out -mcpu=cortex-a9 or replacing -Os
with any other optimization level.

Reproducable with arm-linux-androideabi, arm-eabi and arm-linux-gnueabi
compilers.

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/7

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On 2012-02-17T10:46:11+00:00 Mikpe wrote:

Fails with gcc 4.7 but works with 4.6, 4.5, and 4.4.

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/8

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On 2012-02-17T23:22:41+00:00 Rearnsha wrote:

Confirmed.
lsls Rd, Rn, Rm
is only 2 bytes in size if Rd == Rn

Although the testcase only fails on trunk, the miscalculation is certain
to be present on all maintained branches.

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/9

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On 2012-02-18T12:27:50+00:00 stevenb wrote:

Richard, I suppose you mean the problem is in this define_insn:

(define_insn "*thumb1_ashlsi3"
  [(set (match_operand:SI            0 "register_operand" "=l,l")
        (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
                   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
  "TARGET_THUMB1"
  "lsl\\t%0, %1, %2"
  [(set_attr "length" "2")
   (set_attr "conds" "set")])

which should set "length" depending on the operands?

(BTW when should ARM_LSL_NAME be used instead of "lsl"? Or is
ARM_LSL_NAME not relevant for Thumb?)

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/10

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On 2012-02-18T12:36:29+00:00 stevenb wrote:

(If the pattern of comment #3 is to blame, then this goes back all the
way to the check-in of that pattern, see
http://gcc.gnu.org/viewcvs?view=revision&revision=33028)

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/11

------------------------------------------------------------------------
On 2012-02-18T12:46:00+00:00 stevenb wrote:

(In reply to comment #4)
> (If the pattern of comment #3 is to blame, then this ...

...probably fix it.

Index: arm.md
===================================================================
--- arm.md      (revision 184318)
+++ arm.md      (working copy)
@@ -3505,7 +3505,12 @@
                   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
   "TARGET_THUMB1"
   "lsl\\t%0, %1, %2"
-  [(set_attr "length" "2")
+  [(set (attr "length")
+       (if_then_else
+        (eq (symbol_ref ("which_alternative"))
+                        (const_int 0))
+        (const_int 4)
+        (const_int 2)))
    (set_attr "conds" "set")])
 
 (define_expand "ashrdi3"


And otherwise: sorry for all the noise :-)

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/12

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On 2012-02-18T12:47:20+00:00 stevenb wrote:

Or better:
Index: arm.md
===================================================================
--- arm.md      (revision 184318)
+++ arm.md      (working copy)
@@ -3505,7 +3505,7 @@
                   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
   "TARGET_THUMB1"
   "lsl\\t%0, %1, %2"
-  [(set_attr "length" "2")
+  [(set_attr "length" "4,2")
    (set_attr "conds" "set")])
 
 (define_expand "ashrdi3"

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/13

------------------------------------------------------------------------
On 2012-02-18T15:25:01+00:00 Rearnsha wrote:

(In reply to comment #3)
> Richard, I suppose you mean the problem is in this define_insn:
> 
> (define_insn "*thumb1_ashlsi3"
>   [(set (match_operand:SI            0 "register_operand" "=l,l")
>         (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
>                    (match_operand:SI 2 "nonmemory_operand" "N,l")))]
>   "TARGET_THUMB1"
>   "lsl\\t%0, %1, %2"
>   [(set_attr "length" "2")
>    (set_attr "conds" "set")])

No, that pattern is only for Thumb1, it never applies to Thumb2.

I'm currently testing a fix

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/14

------------------------------------------------------------------------
On 2012-02-21T15:38:40+00:00 Rearnsha wrote:

Author: rearnsha
Date: Tue Feb 21 15:38:35 2012
New Revision: 184442

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184442
Log:
        PR target/52294
        * thumb2.md (thumb2_shiftsi3_short): Split register and         
        immediate shifts.  For register shifts tie operands 0 and 1.
        (peephole2 for above): Check that register-controlled shifts
        have suitably tied operands.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arm/thumb2.md

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/15

------------------------------------------------------------------------
On 2012-02-21T23:46:10+00:00 Rearnsha wrote:

Author: rearnsha
Date: Tue Feb 21 23:46:05 2012
New Revision: 184452

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184452
Log:
        PR target/52294
        * thumb2.md (thumb2_shiftsi3_short): Split register and
        immediate shifts.  For register shifts tie operands 0 and 1.
        (peephole2 for above): Check that register-controlled shifts
        have suitably tied operands.

Modified:
    branches/gcc-4_6-branch/gcc/ChangeLog
    branches/gcc-4_6-branch/gcc/config/arm/thumb2.md

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/16

------------------------------------------------------------------------
On 2012-02-21T23:51:21+00:00 Rearnsha wrote:

Author: rearnsha
Date: Tue Feb 21 23:51:16 2012
New Revision: 184454

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184454
Log:
        PR target/52294
        * thumb2.md (thumb2_shiftsi3_short): Split register and
        immediate shifts.  For register shifts tie operands 0 and 1.
        (peephole2 for above): Check that register-controlled shifts
        have suitably tied operands.

Modified:
    branches/gcc-4_5-branch/gcc/ChangeLog
    branches/gcc-4_5-branch/gcc/config/arm/thumb2.md

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/17

------------------------------------------------------------------------
On 2012-02-22T00:11:27+00:00 Rearnsha wrote:

Fixed in 4.5, 4.6 and trunk

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/18

------------------------------------------------------------------------
On 2012-06-08T08:57:59+00:00 Jye2 wrote:

Author: jye2
Date: Fri Jun  8 08:57:53 2012
New Revision: 188332

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=188332
Log:
2012-06-08  Joey Ye  <joey...@arm.com>

        Backport r184442 from mainline
        2012-02-21  Richard Earnshaw  <rearn...@arm.com>

        PR target/52294
        * thumb2.md (thumb2_shiftsi3_short): Split register and         
        immediate shifts.  For register shifts tie operands 0 and 1.
        (peephole2 for above): Check that register-controlled shifts
        have suitably tied operands.

        Backport r183756 from mainline
        2012-01-31  Matthew Gretton-Dann  <matthew.gretton-d...@arm.com>

        * config/arm/thumb2.md (thumb2_mov_notscc): Use MVN for true
        condition.

        Backport r183349 from mainline
        2012-01-20  Jakub Jelinek  <ja...@redhat.com>

        PR target/51915
        * config/arm/arm.c (arm_count_output_move_double_insns): Call
        output_move_double on a copy of operands array.

        Backport r183095 from mainline
        2012-01-11  Matthew Gretton-Dann  <matthew.gretton-d...@arm.com>

        * config/arm/arm.md (mov_notscc): Use MVN for false condition.

        Backport r182628 from mainline
        2011-12-21  Richard Earnshaw  <rearn...@arm.com>

        PR target/51643
        * arm.c (arm_function_ok_for_sibcall): Use DECL_WEAK in previous
        change.

        Backport r182621 from mainline
        2011-12-21  Richard Earnshaw  <rearn...@arm.com>

        PR target/51643
        * arm.c (arm_function_ok_for_sibcall): Don't try to tailcall a
        weak function on bare-metal EABI targets.

Testsuite:
        Backport r183349 from mainline
        2012-01-20  Jakub Jelinek  <ja...@redhat.com>

        PR target/51915
        * gcc.target/arm/pr51915.c: New test.

        Backport r183095 from mainline
        2012-01-11  Matthew Gretton-Dann  <matthew.gretton-d...@arm.com>

        * gcc.c-torture/execute/20120110-1.c: New testcase.

        Backport r182621 from mainline
        2011-12-21  Richard Earnshaw  <rearn...@arm.com>

        PR target/51643
        * gcc.target/arm/sibcall-2.c: New test.


Added:
    
branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.c-torture/execute/20120111-1.c
    branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.target/arm/pr51915.c
    branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.target/arm/sibcall-2.c
Modified:
    branches/ARM/embedded-4_6-branch/gcc/ChangeLog.arm
    branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.c
    branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.md
    branches/ARM/embedded-4_6-branch/gcc/config/arm/thumb2.md
    branches/ARM/embedded-4_6-branch/gcc/testsuite/ChangeLog.arm

Reply at: https://bugs.launchpad.net/gcc/+bug/926855/comments/23


** Changed in: gcc
       Status: Unknown => Fix Released

** Changed in: gcc
   Importance: Unknown => Medium

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Title:
  [ARMhf] gcc produces assembler it can't compile

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