> -----Original Message----- > From: Albert ARIBAUD [mailto:albert.u.b...@aribaud.net] > Sent: 05 November 2012 05:02 > To: U-Boot > Cc: Prafulla Wadaskar; Simon Guinot; Albert ARIBAUD > Subject: [PATCH v4 4/4] ARM: lacie_kw: add support for WIRELESS_SPACE > > Signed-off-by: Albert ARIBAUD <albert.u.b...@aribaud.net> > --- > Changes in v4: > - switched from netspace_V2-based to standalone board > - added support for mv88e61xx switch > - corrected some kwbimage.cfg values > > Changes in v3: > - fix broken support for NETSPACE_(MINI|LITE)_V2 > > Changes in v2: > - split the patch in two: mvgbe phy/port changes and WS support. > - removed spurious DEBUG define > - fixed various checkpatch errors/warnings/typos > > board/LaCie/wireless_space/Makefile | 46 +++++++ > board/LaCie/wireless_space/kwbimage.cfg | 190 > +++++++++++++++++++++++++++ > board/LaCie/wireless_space/wireless_space.c | 165 > +++++++++++++++++++++++ > boards.cfg | 1 + > include/configs/wireless_space.h | 183 > ++++++++++++++++++++++++++ > 5 files changed, 585 insertions(+) > create mode 100644 board/LaCie/wireless_space/Makefile > create mode 100644 board/LaCie/wireless_space/kwbimage.cfg > create mode 100644 board/LaCie/wireless_space/wireless_space.c > create mode 100644 include/configs/wireless_space.h > > diff --git a/board/LaCie/wireless_space/Makefile > b/board/LaCie/wireless_space/Makefile > new file mode 100644 > index 0000000..b43c3d3 > --- /dev/null > +++ b/board/LaCie/wireless_space/Makefile > @@ -0,0 +1,46 @@ > +# > +# Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > +# > +# Based on Kirkwood support: > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > + > +include $(TOPDIR)/config.mk > +ifneq ($(OBJTREE),$(SRCTREE)) > +$(shell mkdir -p $(obj)../common) > +endif > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := $(BOARD).o ../common/common.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +##################################################################### > #### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +##################################################################### > #### > diff --git a/board/LaCie/wireless_space/kwbimage.cfg > b/board/LaCie/wireless_space/kwbimage.cfg > new file mode 100644 > index 0000000..a5b200f > --- /dev/null > +++ b/board/LaCie/wireless_space/kwbimage.cfg > @@ -0,0 +1,190 @@ > +# > +# Copyright (C) 2012 Albert ARIBAUD <albert.u.b...@aribaud.net> > +# > +# Based on netspace_v2 kwbimage.cfg: > +# Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > +# > +# Based on Kirkwood support: > +# (C) Copyright 2009 > +# Marvell Semiconductor <www.marvell.com> > +# Written-by: Prafulla Wadaskar <prafu...@marvell.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# Refer docs/README.kwimage for more details about how-to configure > +# and create kirkwood boot image > +# > + > +# Boot Media configurations > +BOOT_FROM nand # Boot from NAND flash > + > +# SOC registers configuration using bootrom header extension > +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed > + > +# Configure RGMII-0 interface pad voltage to 1.8V > +DATA 0xFFD100e0 0x1B1B1B9B > + > +#Dram initalization for SINGLE x16 CL=5 @ 400MHz > +DATA 0xFFD01400 0x43000618 # DDR Configuration register > +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) > +# bit23-14: zero > +# bit24: 1= enable exit self refresh mode on DDR access > +# bit25: 1 required > +# bit29-26: zero > +# bit31-30: 01 > + > +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low > +# bit 4: 0=addr/cmd in smame cycle > +# bit 5: 0=clk is driven during self refresh, we don't care for > APX > +# bit 6: 0=use recommended falling edge of clk for addr/cmd > +# bit14: 0=input buffer always powered up > +# bit18: 1=cpu lock transaction enabled > +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled > bit31=0 > +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, > unbuffered DIMM > +# bit30-28: 3 required > +# bit31: 0=no additional STARTBURST delay > + > +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value > +1) > +# bit7-4: TRCD > +# bit11- 8: TRP > +# bit15-12: TWR > +# bit19-16: TWTR > +# bit20: TRAS msb > +# bit23-21: 0x0 > +# bit27-24: TRRD > +# bit31-28: TRTP > + > +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) > +# bit6-0: TRFC > +# bit8-7: TR2R > +# bit10-9: TR2W > +# bit12-11: TW2W > +# bit31-13: zero required > + > +DATA 0xFFD01410 0x0000CCCC # DDR Address Control > +# bit1-0: 00, Cs0width=x8 > +# bit3-2: 11, Cs0size=1Gb > +# bit5-4: 00, Cs2width=x8 > +# bit7-6: 00, Cs1size=1Gb > +# bit9-8: 00, Cs2width=x8 > +# bit11-10: 00, Cs2size=1Gb > +# bit13-12: 00, Cs3width=x8 > +# bit15-14: 00, Cs3size=1Gb > +# bit16: 0, Cs0AddrSel > +# bit17: 0, Cs1AddrSel > +# bit18: 0, Cs2AddrSel > +# bit19: 0, Cs3AddrSel > +# bit31-20: 0 required > + > +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control > +# bit0: 0, OpenPage enabled > +# bit31-1: 0 required > + > +DATA 0xFFD01418 0x00000000 # DDR Operation > +# bit3-0: 0x0, DDR cmd > +# bit31-4: 0 required > + > +DATA 0xFFD0141C 0x00000632 # DDR Mode > +# bit2-0: 2, BurstLen=2 required > +# bit3: 0, BurstType=0 required > +# bit6-4: 4, CL=5 > +# bit7: 0, TestMode=0 normal > +# bit8: 0, DLL reset=0 normal > +# bit11-9: 6, auto-precharge write recovery ???????????? > +# bit12: 0, PD must be zero > +# bit31-13: 0 required > + > +DATA 0xFFD01420 0x00000004 # DDR Extended Mode > +# bit0: 0, DDR DLL enabled > +# bit1: 1, DDR drive strenght reduced > +# bit2: 1, DDR ODT control lsd enabled > +# bit5-3: 000, required > +# bit6: 1, DDR ODT control msb, enabled > +# bit9-7: 000, required > +# bit10: 0, differential DQS enabled > +# bit11: 0, required > +# bit12: 0, DDR output buffer enabled > +# bit31-13: 0 required > + > +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High > +# bit2-0: 111, required > +# bit3 : 1 , MBUS Burst Chop disabled > +# bit6-4: 111, required > +# bit7 : 1 , D2P Latency enabled > +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= > 300MHz > +# bit9 : 0 , no half clock cycle addition to dataout > +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals > +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh > +# bit15-12: 1111 required > +# bit31-16: 0 required > + > +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) > +# bit3-0: 0000, required > +# bit7-4: 0010, 2 cycle from read command to M_ODT high > +# bit11-8: 0101, 5 cycles from read command to M_ODT low > +# bit15-12: 0101, 5 cycles from read command to internal ODT high > +# bit19-16: 1000, 8 cycles from read command to internal ODT low > +# bit31-20: 0..0, required > + > +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) > +# bit3-0: 0010, 2 cycle from write command to M_ODT high > +# bit7-4: 0101, 5 cycles write read command to M_ODT low > +# bit11-8: 0101, 5 cycles write read command to internal ODT high > +# bit15-12: 1000, 8 cycles write read command to internal ODT low > +# bit31-16: 0..0, required > + > +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 > +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size > +# bit0: 1, Window enabled > +# bit1: 0, Write Protect disabled > +# bit3-2: 00, CS0 hit selected > +# bit23-4: ones, required > +# bit31-24: 0x07, Size (i.e. 128MB) > + > +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled > +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled > +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled > + > +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) > +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 > +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 > + > +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) > +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above > +# bit3-2: 01, ODT1 active NEVER! > +# bit31-4: zero, required > + > +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control > +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM > bank0 > +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM > bank0 > +# bit11-10:1, DQ_ODTSel. ODT select turned on > + > +DATA 0xFFD01480 0x00000001 # DDR Initialization Control > +#bit0=1, enable DDR init upon this register write > + > +0xFFD10000 0x01111111 # MPP control 0 register > +0xFFD10004 0x00003311 # MPP control 1 register > +0xFFD10008 0x33331100 # MPP control 2 register > +0xFFD1000C 0x33333333 # MPP control 3 register > +0xFFD10010 0x33330000 # MPP control 4 register > +0xFFD10014 0x00000000 # MPP control 5 register > +0xFFD10018 0x00000000 # MPP control 6 register > + > +0xFFD10104 0xFF006808 # GPIO LO OE > +0xFFD10100 0x00000000 # GPIO LO EN > +0xFFD10144 0x0000F989 # GPIO HI OE > +0xFFD10140 0x00000000 # GPIO HI EN > + > +# End of Header extension > +DATA 0x0 0x0 > diff --git a/board/LaCie/wireless_space/wireless_space.c > b/board/LaCie/wireless_space/wireless_space.c > new file mode 100644 > index 0000000..930d19f > --- /dev/null > +++ b/board/LaCie/wireless_space/wireless_space.c > @@ -0,0 +1,165 @@ > +/* > + * Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > + * > + * Based on Kirkwood support: > + * (C) Copyright 2009 > + * Marvell Semiconductor <www.marvell.com> > + * Written-by: Prafulla Wadaskar <prafu...@marvell.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <common.h> > +#include <command.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/kirkwood.h> > +#include <asm/arch/mpp.h> > +#include <asm/arch/gpio.h> > + > +#include "../common/common.h" > +#include "netdev.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* GPIO configuration */ > + > +#define WIRELESS_SPACE_OE_LOW 0xFF006808 > +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 > +#define WIRELESS_SPACE_OE_VAL_LOW 0x00000000 > +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000000 > + > +#define WIRELESS_SPACE_GPIO_BUTTON 43 > + > +const u32 kwmpp_config[] = { > + MPP0_NF_IO2, > + MPP1_NF_IO3, > + MPP2_NF_IO4, > + MPP3_NF_IO5, > + MPP4_NF_IO6, > + MPP5_NF_IO7, > + MPP6_SYSRST_OUTn, > + MPP7_GPO, /* Fan speed (bit 1) */ > + MPP8_TW_SDA, > + MPP9_TW_SCK, > + MPP10_UART0_TXD, > + MPP11_UART0_RXD, > + MPP13_GPIO, /* Red led */ > + MPP14_GPIO, /* USB fuse */ > + MPP15_SATA0_ACTn, > + MPP16_GPIO, /* SATA 0 power */ > + MPP17_GPIO, /* SATA 1 power */ > + MPP18_NF_IO0, > + MPP19_NF_IO1, > + MPP20_GE1_0, /* Gigabit Ethernet 1 */ > + MPP21_GE1_1, > + MPP22_GE1_2, > + MPP23_GE1_3, > + MPP24_GE1_4, > + MPP25_GE1_5, > + MPP26_GE1_6, > + MPP27_GE1_7, > + MPP28_GE1_8, > + MPP29_GE1_9, > + MPP30_GE1_10, > + MPP31_GE1_11, > + MPP32_GE1_12, > + MPP33_GE1_13, > + MPP34_GE1_14, > + MPP35_GE1_15, > + MPP36_GPIO, /* Fan speed (bit 2) */ > + MPP37_GPIO, /* Fan speed (bit 0) */ > + MPP38_GPIO, /* Fan power */ > + MPP39_GPIO, /* Fan rotation fail */ > + MPP40_GPIO, /* Ethernet switch link */ > + MPP41_GPIO, /* USB enable host vbus */ > + MPP42_GPIO, /* LED clock control */ > + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ > + MPP44_GPIO, /* Red LED on/off */ > + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ > + MPP46_GPIO, /* Green LED on/off */ > + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ > + MPP48_GPIO, /* Blue LED on/off */ > + 0 > +}; > + > +struct mv88e61xx_config swcfg = { > + .name = "egiga0", > + .vlancfg = MV88E61XX_VLANCFG_SWITCH, > + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, > + .led_init = MV88E61XX_LED_INIT_DIS, > + .mdip = MV88E61XX_MDIP_NOCHANGE, > + .portstate = MV88E61XX_PORTSTT_FORWARDING, > + .cpuport = 0x30, > + .ports_enabled = 0x37, > +}; > + > +int board_early_init_f(void) > +{ > + /* Gpio configuration */ > + kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, > WIRELESS_SPACE_OE_VAL_HIGH, > + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); > + > + /* Multi-Purpose Pins Functionality configuration */ > + kirkwood_mpp_conf(kwmpp_config, NULL); > + > + return 0; > +} > + > +int board_init(void) > +{ > + /* Machine number */ > + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; > + > + /* Boot parameters address */ > + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; > + > + return 0; > +} > + > +#if defined(CONFIG_MISC_INIT_R) > +int misc_init_r(void) > +{ > +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) > + if (!getenv("ethaddr")) { > + uchar mac[6]; > + if (lacie_read_mac_address(mac) == 0) > + eth_setenv_enetaddr("ethaddr", mac); > + } > +#endif > + return 0; > +} > +#endif > + > +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) > +/* Configure and initialize PHY */ > +void reset_phy(void) > +{ > + /* configure true PHY on egiga1 */ > + mv_phy_88e1116_init("egiga1", CONFIG_EGIGA1_PHY); > + /* configure switch on egiga0 */ > + mv88e61xx_switch_initialize(&swcfg); > +} > +#endif > + > +#if defined(CONFIG_KIRKWOOD_GPIO) > +/* Return GPIO button status */ > +static int > +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const > argv[]) > +{ > + return kw_gpio_get_value(WIRELESS_SPACE_GPIO_BUTTON); > +} > + > +U_BOOT_CMD(button, 1, 1, do_read_button, > + "Return GPIO button status 0=off 1=on", ""); > +#endif > diff --git a/boards.cfg b/boards.cfg > index 25c53d4..b91cdd9 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -168,6 +168,7 @@ netspace_lite_v2 arm arm926ejs > netspace_v2 LaCie > netspace_max_v2 arm arm926ejs netspace_v2 > LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 > netspace_mini_v2 arm arm926ejs netspace_v2 > LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 > netspace_v2 arm arm926ejs netspace_v2 > LaCie kirkwood lacie_kw:NETSPACE_V2 > +wireless_space arm arm926ejs wireless_space > LaCie kirkwood > dreamplug arm arm926ejs - > Marvell kirkwood > guruplug arm arm926ejs - > Marvell kirkwood > mv88f6281gtw_ge arm arm926ejs - > Marvell kirkwood > diff --git a/include/configs/wireless_space.h > b/include/configs/wireless_space.h > new file mode 100644 > index 0000000..02a8c30 > --- /dev/null > +++ b/include/configs/wireless_space.h > @@ -0,0 +1,183 @@ > +/* > + * Copyright (C) 2011 Albert ARIBAUD <albert.u.b...@aribaud.net> > + * > + * Based on the netspace_v2 code which is > + * Copyright (C) 2011 Simon Guinot <sgui...@lacie.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef _CONFIG_WIRELESS_SPACE_H > +#define _CONFIG_WIRELESS_SPACE_H > + > +/* > + * Machine number definition > + */ > +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h > */ > +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE > +#define CONFIG_IDENT_STRING " Wireless Space" > + > +/* > + * High Level Configuration Options (easy to change) > + */ > +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ > +#define CONFIG_KIRKWOOD /* SoC Family Name */ > +/* SoC name */ > +#define CONFIG_KW88F6281 > +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ > + > +/* > + * Commands configuration > + */ > +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ > +#include <config_cmd_default.h> > +#define CONFIG_CMD_ENV > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_I2C > +#define CONFIG_CMD_IDE > +#define CONFIG_CMD_USB > + > +/* > + * Core clock definition > + */ > +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ > + > +/* > + * SDRAM configuration > + */ > +#define CONFIG_NR_DRAM_BANKS 1 > + > +/* > + * Different SDRAM configuration and size for some of the boards > derived > + * from the Network Space v2 > + */ > + > +/* > + * mv-common.h should be defined after CMD configs since it used them > + * to enable certain macros > + */ > +#include "mv-common.h" > + > +/* Remove or override few declarations from mv-common.h */ > +#undef CONFIG_RBTREE > +#undef CONFIG_SYS_IDE_MAXBUS > +#undef CONFIG_SYS_IDE_MAXDEVICE > +#define CONFIG_SYS_IDE_MAXBUS 1 > +#define CONFIG_SYS_IDE_MAXDEVICE 1 > +#undef CONFIG_SYS_PROMPT > +#define CONFIG_SYS_PROMPT "ws> " > + > +/* > + * Ethernet Driver configuration > + */ > +#ifdef CONFIG_CMD_NET > +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address > */ > +#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ > +#define CONFIG_EGIGA1_PHY 0x6 /* egiga1 has a true PHY */ > +#define CONFIG_MVGBE_PHY_ADRS {0xa, 0x6} /* egiga0 has a ('false') > PHY */ > +#define CONFIG_MII > +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN > +#define CONFIG_NETCONSOLE > +#define CONFIG_MV88E61XX_SWITCH > +#endif /* CONFIG_CMD_NET */ > + > +/* > + * SATA Driver configuration > + */ > +#ifdef CONFIG_MVSATA_IDE > +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET > +#endif /* CONFIG_MVSATA_IDE */ > + > +/* > + * Enable GPI0 support > + */ > +#define CONFIG_KIRKWOOD_GPIO > + > +/* > + * Enable I2C support > + */ > +#ifdef CONFIG_CMD_I2C > +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ > +#define CONFIG_CMD_EEPROM > +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 > +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ > +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device > address */ > +#endif /* CONFIG_CMD_I2C */ > + > +/* > + * Partition support > + */ > +#define CONFIG_DOS_PARTITION > +#define CONFIG_EFI_PARTITION > + > +/* > + * File systems support > + */ > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > + > +/* > + * Use the HUSH parser > + */ > +#define CONFIG_SYS_HUSH_PARSER > + > +/* > + * Console configuration > + */ > +#define CONFIG_CONSOLE_MUX > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > + > +/* > + * Enable device tree support > + */ > +#define CONFIG_OF_LIBFDT > + > +/* > + * Environment variables configurations > + */ > + > +#define CONFIG_ENV_IS_IN_NAND > +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ > +#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ > +#define CONFIG_ENV_ADDR 0x70000 > +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ > + > +/* > + * Default environment variables > + */ > +#define CONFIG_BOOTARGS "console=ttyS0,115200" > + > +#define CONFIG_BOOTCOMMAND \ > + "dhcp && run netconsole; " \ > + "if run usbload || run diskload; then bootm; fi" > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "stdin=serial\0" \ > + "stdout=serial\0" \ > + "stderr=serial\0" \ > + "bootfile=uImage\0" \ > + "loadaddr=0x800000\0" \ > + "autoload=no\0" \ > + "netconsole=" \ > + "set stdin $stdin,nc; " \ > + "set stdout $stdout,nc; " \ > + "set stderr $stderr,nc;\0" \ > + "diskload=ide reset && " \ > + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ > + "usbload=usb start && " \ > + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" > + > +#endif /* _CONFIG_WIRELESS_SPACE_H */ > --
Looks okay to me. Acked-by: Prafulla Wadaskar <prafu...@marvell.com> Will pull entire patch series in next week. Regards... Prafulla . . . > 1.7.9.5 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
