From: Stefan Reinauer <reina...@chromium.org>
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).
Signed-off-by: Stefan Reinauer <reina...@chromium.org>
Signed-off-by: Simon Glass <s...@chromium.org>
---
arch/x86/cpu/coreboot/coreboot.c | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index b942a3e..d1be8ff 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -26,6 +26,8 @@
#include <asm/u-boot-x86.h>
#include <flash.h>
#include <netdev.h>
+#include <asm/msr.h>
+#include <asm/cache.h>
#include <asm/arch-coreboot/tables.h>
#include <asm/arch-coreboot/sysinfo.h>
#include <asm/arch/timestamp.h>
@@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis)
void setup_pcat_compatibility()
{
}
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+int board_final_cleanup(void)
+{
+ /* Un-cache the ROM so the kernel has one
+ * more MTRR available.
+ */
+ disable_cache();
+ wrmsr(MTRRphysBase_MSR(7), 0);
+ wrmsr(MTRRphysMask_MSR(7), 0);
+ enable_cache();
+
+ return 0;
+}
--
1.7.7.3
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