On Thu, Sep 13, 2012 at 12:38:16PM -0700, Tom Rini wrote: > From: Pankaj Bharadiya <pankaj.bharad...@ti.com> > > The endpoint rx count register value will be zero if it is read before > receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set. > > Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before > reading endpoint rx count register. Proceed with rx count read and > FIFO read only if RXPKTRDY bit is set. > > Signed-off-by: Pankaj Bharadiya <pankaj.bharad...@ti.com> > Signed-off-by: Tom Rini <tr...@ti.com>
Applied to u-boot-ti/master, thanks! -- Tom
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