Hi Simon,
On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <s...@chromium.org> wrote:
> From: Gabe Black <gabebl...@chromium.org>
>
> A hook is installed to configure PCI bus bridges as they encountered by
> u-boot.
> The hook extracts the secondary bus number from the bridge's config space and
> then recursively scans that bus.
>
> On Coreboot, the PCI bus address space has identity mapping with the
> physical address space, so declare it as such to ensure that the "pci_map_bar"
> function used by some PCI drivers is behaving properly. This fixes the
> EHCI PCI driver initialization on Stumpy.
>
> This was tested as follows:
>
> Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
> bus 1, and empty busses 2 through 5. This matches the bridges
> reported on bus 0 and the PCI configuration output from coreboot.
>
> Signed-off-by: Gabe Black <gabebl...@chromium.org>
> Signed-off-by: Vincent Palatin <vpala...@chromium.org>
> Signed-off-by: Stefan Reinauer <reina...@chromium.org>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> arch/x86/cpu/coreboot/pci.c | 26 +++++++++++++++++++++++---
> 1 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
> index 0ddc975..8f94167 100644
> --- a/arch/x86/cpu/coreboot/pci.c
> +++ b/arch/x86/cpu/coreboot/pci.c
> @@ -31,15 +31,35 @@
>
> static struct pci_controller coreboot_hose;
>
> +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
> + struct pci_config_table *table)
> +{
> + u8 secondary;
> + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
> + hose->last_busno = max(hose->last_busno, secondary);
> + pci_hose_scan_bus(hose, secondary);
> +}
> +
> +static struct pci_config_table pci_coreboot_config_table[] = {
> + /* vendor, device, class, bus, dev, func */
> + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
> + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
> + {}
> +};
> +
> void pci_init_board(void)
> {
> + coreboot_hose.config_table = pci_coreboot_config_table;
> coreboot_hose.first_busno = 0;
> - coreboot_hose.last_busno = 0xff;
> - coreboot_hose.region_count = 0;
> + coreboot_hose.last_busno = 0;
> +
> + pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
> + PCI_REGION_MEM);
> + coreboot_hose.region_count = 1;
>
> pci_setup_type1(&coreboot_hose);
>
> pci_register_hose(&coreboot_hose);
>
> - coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
> + pci_hose_scan(&coreboot_hose);
> }
> --
> 1.7.7.3
>
Acked-by: Graeme Russ <graeme.r...@gmail.com>
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
