Hi dingu...@altera.com, On Wed, 3 Oct 2012 15:38:01 -0600, <dingu...@altera.com> wrote:
> From: Dinh Nguyen <dingu...@altera.com> > > Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. > > Signed-off-by: Dinh Nguyen <dingu...@altera.com> > Signed-off-by: Chin Liang See <cl...@altera.com> > Signed-off-by: Pavel Machek <pa...@denx.de> > Reviewed-by: Marek Vasut <ma...@denx.de> > Acked-by: Tom Trini <tr...@ti.com> > Cc: Wolfgang Denx <w...@denx.de> > Cc: Albert Aribaud <albert.u.b...@aribaud.net> > Cc: Stefan Roese <s...@denx.de> > ---- > v7: fix build warning in spl.c:45:38 > > Based on v2012.10-rc2 > --- > MAINTAINERS | 5 + > arch/arm/cpu/armv7/socfpga/Makefile | 51 +++++ > arch/arm/cpu/armv7/socfpga/config.mk | 16 ++ > arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 77 +++++++ > arch/arm/cpu/armv7/socfpga/misc.c | 54 +++++ > arch/arm/cpu/armv7/socfpga/spl.c | 48 ++++ > arch/arm/cpu/armv7/socfpga/timer.c | 105 +++++++++ > arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 60 +++++ > arch/arm/include/asm/arch-socfpga/reset_manager.h | 37 +++ > .../include/asm/arch-socfpga/socfpga_base_addrs.h | 27 +++ > arch/arm/include/asm/arch-socfpga/spl.h | 26 +++ > arch/arm/include/asm/arch-socfpga/timer.h | 29 +++ > board/altera/socfpga_cyclone5/Makefile | 50 +++++ > board/altera/socfpga_cyclone5/socfpga_cyclone5.c | 80 +++++++ > boards.cfg | 1 + > include/common.h | 2 +- > include/configs/socfpga_cyclone5.h | 236 > ++++++++++++++++++++ > 17 files changed, 903 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile > create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk > create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S > create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c > create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c > create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c > create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds > create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h > create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h > create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h > create mode 100644 board/altera/socfpga_cyclone5/Makefile > create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c > create mode 100644 include/configs/socfpga_cyclone5.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index aa54fe1..ee8cfb0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -777,6 +777,11 @@ Nagendra T S <nagen...@mistralsolutions.com> > > am3517_crane ARM ARMV7 (AM35x SoC) > > +Dinh Nguyen <dingu...@altera.com> > +Chin Liang See <cl...@altera.com> > + > + socfpga socfpga_cyclone5 > + > Sandeep Paulraj <s-paul...@ti.com> > > davinci_dm355evm ARM926EJS > diff --git a/arch/arm/cpu/armv7/socfpga/Makefile > b/arch/arm/cpu/armv7/socfpga/Makefile > new file mode 100644 > index 0000000..376a4bd > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/Makefile > @@ -0,0 +1,51 @@ > +# > +# (C) Copyright 2000-2003 > +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > +# > +# Copyright (C) 2012 Altera Corporation <www.altera.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(SOC).o > + > +SOBJS := lowlevel_init.o > +COBJS-y := misc.o timer.o > +COBJS-$(CONFIG_SPL_BUILD) += spl.o > + > +COBJS := $(COBJS-y) > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > + > +all: $(obj).depend $(LIB) > + > +$(LIB): $(OBJS) > + $(call cmd_link_o_target, $(OBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/arch/arm/cpu/armv7/socfpga/config.mk > b/arch/arm/cpu/armv7/socfpga/config.mk > new file mode 100644 > index 0000000..b72ed1e > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/config.mk > @@ -0,0 +1,16 @@ > +# > +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed "as is" WITHOUT ANY WARRANTY of any > +# kind, whether express or implied; without even the implied warranty > +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +ifndef CONFIG_SPL_BUILD > +ALL-y += $(obj)u-boot.img > +endif > diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S > b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S > new file mode 100644 > index 0000000..001b37d > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S > @@ -0,0 +1,77 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include <config.h> > +#include <version.h> > + > +/* Save the parameter pass in by previous boot loader */ > +.global save_boot_params > +save_boot_params: > + /* save the parameter here */ > + > + /* > + * Setup stack for exception, which is located > + * at the end of on-chip RAM. We don't expect exception prior to > + * relocation and if that happens, we won't worry -- it will overide > + * global data region as the code will goto reset. After relocation, > + * this region won't be used by other part of program. > + * Hence it is safe. > + */ > + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) > + ldr r1, =IRQ_STACK_START_IN > + str r0, [r1] > + > + bx lr > + > + > +/* Set up the platform, once the cpu has been initialized */ > +.globl lowlevel_init > +lowlevel_init: > + > + /* Remap */ > +#ifdef CONFIG_SPL_BUILD > + /* > + * SPL : configure the remap (L3 NIC-301 GPV) > + * so the on-chip RAM at lower memory instead ROM. > + */ > + ldr r0, =SOCFPGA_L3REGS_ADDRESS > + mov r1, #0x19 > + str r1, [r0] > +#else > + /* > + * U-Boot : configure the remap (L3 NIC-301 GPV) > + * so the SDRAM at lower memory instead on-chip RAM. > + */ > + ldr r0, =SOCFPGA_L3REGS_ADDRESS > + mov r1, #0x2 > + str r1, [r0] > + > + /* Private components security */ > + > + /* > + * U-Boot : configure private timer, global timer and cpu > + * component access as non secure for kernel stage (as required > + * by kernel) > + */ > + mrc p15,4,r0,c15,c0,0 > + add r1, r0, #0x54 > + ldr r2, [r1] > + orr r2, r2, #0xff > + orr r2, r2, #0xf00 > + str r2, [r1] > +#endif /* #ifdef CONFIG_SPL_BUILD */ > + mov pc, lr > diff --git a/arch/arm/cpu/armv7/socfpga/misc.c > b/arch/arm/cpu/armv7/socfpga/misc.c > new file mode 100644 > index 0000000..fa16424 > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/misc.c > @@ -0,0 +1,54 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/reset_manager.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct socfpga_reset_manager *reset_manager_base = > + (void *)SOCFPGA_RSTMGR_ADDRESS; > + > +/* > + * Write the reset manager register to cause reset > + */ > +void reset_cpu(ulong addr) > +{ > + /* request a warm reset */ > + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); > + /* > + * infinite loop here as watchdog will trigger and reset > + * the processor > + */ > + while (1) > + ; > +} > + > +/* > + * Release peripherals from reset based on handoff > + */ > +void reset_deassert_peripherals_handoff(void) > +{ > + writel(0, &reset_manager_base->per_mod_reset); > +} > + > +int dram_init(void) > +{ > + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); > + return 0; > +} > diff --git a/arch/arm/cpu/armv7/socfpga/spl.c > b/arch/arm/cpu/armv7/socfpga/spl.c > new file mode 100644 > index 0000000..944238b > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/spl.c > @@ -0,0 +1,48 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/u-boot.h> > +#include <asm/utils.h> > +#include <version.h> > +#include <image.h> > +#include <malloc.h> > +#include <asm/arch/reset_manager.h> > +#include <spl.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +u32 spl_boot_device(void) > +{ > + return BOOT_DEVICE_RAM; > +} > + > +/* > + * Board initialization after bss clearance > + */ > +void spl_board_init(void) > +{ > + /* init timer for enabling delay function */ > + timer_init(); > + > + /* de-assert reset for peripherals and bridges based on handoff */ > + reset_deassert_peripherals_handoff(); > + > + /* enable console uart printing */ > + preloader_console_init(); > +} > diff --git a/arch/arm/cpu/armv7/socfpga/timer.c > b/arch/arm/cpu/armv7/socfpga/timer.c > new file mode 100644 > index 0000000..79fa081 > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/timer.c > @@ -0,0 +1,105 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/timer.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; > + > +/* > + * Timer initialization > + */ > +int timer_init(void) > +{ > + writel(TIMER_LOAD_VAL, &timer_base->load_val); > + writel(TIMER_LOAD_VAL, &timer_base->curr_val); > + writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); > + return 0; > +} > + > +static u32 read_timer(void) > +{ > + return readl(&timer_base->curr_val); > +} > + > +/* > + * Delay x useconds > + */ > +void __udelay(unsigned long usec) > +{ > + unsigned long now, last; > + /* > + * get the tmo value based on timer clock speed > + * tmo = delay required / period of timer clock > + */ > + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; > + > + last = read_timer(); > + while (tmo > 0) { > + now = read_timer(); > + if (last >= now) > + /* normal mode (non roll) */ > + tmo -= last - now; > + else > + /* we have overflow of the count down timer */ > + tmo -= TIMER_LOAD_VAL - last + now; > + last = now; > + } > +} > + > +/* > + * Get the timer value > + */ > +ulong get_timer(ulong base) > +{ > + return get_timer_masked() - base; > +} > + > +/* > + * Timer : get the time difference > + * Unit of tick is based on the CONFIG_SYS_HZ > + */ > +ulong get_timer_masked(void) > +{ > + /* current tick value */ > + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); > + if (gd->lastinc >= now) { > + /* normal mode (non roll) */ > + /* move stamp forward with absolute diff ticks */ > + gd->tbl += gd->lastinc - now; > + } else { > + /* we have overflow of the count down timer */ > + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; > + } > + gd->lastinc = now; > + return gd->tbl; > +} > + > +/* > + * Reset the timer > + */ > +void reset_timer(void) > +{ > + /* capture current decrementer value time */ > + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); > + /* start "advancing" time stamp from 0 */ > + gd->tbl = 0; > +} > + > diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds > b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds > new file mode 100644 > index 0000000..7cd409c > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds > @@ -0,0 +1,60 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } > + > +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") > +OUTPUT_ARCH(arm) > +ENTRY(_start) > +SECTIONS > +{ > + . = 0x00000000; > + > + . = ALIGN(4); > + .text : > + { > + arch/arm/cpu/armv7/start.o (.text) > + *(.text*) > + } >.sdram > + > + . = ALIGN(4); > + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram > + > + . = ALIGN(4); > + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram > + > + . = ALIGN(4); > + __image_copy_end = .; > + _end = .; > + > + .bss : { > + . = ALIGN(4); > + __bss_start = .; > + *(.bss*) > + . = ALIGN(4); > + __bss_end__ = .; > + } >.sdram > + > + . = ALIGN(8); > + __malloc_start = .; > + . = . + CONFIG_SPL_MALLOC_SIZE; > + __malloc_end = .; > + > + . = . + CONFIG_SPL_STACK_SIZE; > + . = ALIGN(8); > + __stack_start = .; > +} > diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h > b/arch/arm/include/asm/arch-socfpga/reset_manager.h > new file mode 100644 > index 0000000..d9d2c1c > --- /dev/null > +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h > @@ -0,0 +1,37 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef _RESET_MANAGER_H_ > +#define _RESET_MANAGER_H_ > + > +void reset_cpu(ulong addr); > +void reset_deassert_peripherals_handoff(void); > + > +struct socfpga_reset_manager { > + u32 padding1; > + u32 ctrl; > + u32 padding2; > + u32 padding3; > + u32 mpu_mod_reset; > + u32 per_mod_reset; > + u32 per2_mod_reset; > + u32 brg_mod_reset; > +}; > + > +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 > + > +#endif /* _RESET_MANAGER_H_ */ > diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > new file mode 100644 > index 0000000..f353eb2 > --- /dev/null > +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h > @@ -0,0 +1,27 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef _SOCFPGA_BASE_ADDRS_H_ > +#define _SOCFPGA_BASE_ADDRS_H_ > + > +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 > +#define SOCFPGA_UART0_ADDRESS 0xffc02000 > +#define SOCFPGA_UART1_ADDRESS 0xffc03000 > +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 > +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 > + > +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ > diff --git a/arch/arm/include/asm/arch-socfpga/spl.h > b/arch/arm/include/asm/arch-socfpga/spl.h > new file mode 100644 > index 0000000..efd0c06 > --- /dev/null > +++ b/arch/arm/include/asm/arch-socfpga/spl.h > @@ -0,0 +1,26 @@ > +/* > + * Copyright (C) 2012 Pavel Machek <pa...@denx.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef _SOCFPGA_SPL_H_ > +#define _SOCFPGA_SPL_H_ > + > +/* Symbols from linker script */ > +extern char __malloc_start, __malloc_end, __stack_start; > + > +#define BOOT_DEVICE_RAM 1 > + > +#endif > diff --git a/arch/arm/include/asm/arch-socfpga/timer.h > b/arch/arm/include/asm/arch-socfpga/timer.h > new file mode 100644 > index 0000000..830c94a > --- /dev/null > +++ b/arch/arm/include/asm/arch-socfpga/timer.h > @@ -0,0 +1,29 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef _SOCFPGA_TIMER_H_ > +#define _SOCFPGA_TIMER_H_ > + > +struct socfpga_timer { > + u32 load_val; > + u32 curr_val; > + u32 ctrl; > + u32 eoi; > + u32 int_stat; > +}; > + > +#endif > diff --git a/board/altera/socfpga_cyclone5/Makefile > b/board/altera/socfpga_cyclone5/Makefile > new file mode 100644 > index 0000000..43bbc37 > --- /dev/null > +++ b/board/altera/socfpga_cyclone5/Makefile > @@ -0,0 +1,50 @@ > +# > +# (C) Copyright 2001-2006 > +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > +# (C) Copyright 2010, Thomas Chou <tho...@wytron.com.tw> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := socfpga_cyclone5.o > + > +SRCS := $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > + > +$(LIB): $(obj).depend $(OBJS) > + $(call cmd_link_o_target, $(OBJS)) > + > +clean: > + rm -f $(OBJS) > + > +distclean: clean > + rm -f $(LIB) core *.bak $(obj).depend > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c > b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c > new file mode 100644 > index 0000000..7725be1 > --- /dev/null > +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c > @@ -0,0 +1,80 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include <common.h> > +#include <asm/arch/reset_manager.h> > +#include <asm/io.h> > + > +#include <netdev.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* > + * Print CPU information > + */ > +int print_cpuinfo(void) > +{ > + puts("CPU : Altera SOCFPGA Platform\n"); > + return 0; > +} > + > +/* > + * Print Board information > + */ > +int checkboard(void) > +{ > + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); > + return 0; > +} > + > +/* > + * Initialization function which happen at early stage of c code > + */ > +int board_early_init_f(void) > +{ > + return 0; > +} > + > +/* > + * Miscellaneous platform dependent initialisations > + */ > +int board_init(void) > +{ > + icache_enable(); > + return 0; > +} > + > +int misc_init_r(void) > +{ > + return 0; > +} > + > +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) > +int overwrite_console(void) > +{ > + return 0; > +} > +#endif > + > +/* > + * DesignWare Ethernet initialization > + */ > +/* We know all the init functions have been run now */ > +int board_eth_init(bd_t *bis) > +{ > + return 0; > +} > diff --git a/boards.cfg b/boards.cfg > index f789539..2388cee 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -272,6 +272,7 @@ ventana arm armv7:arm720t > ventana nvidia > whistler arm armv7:arm720t whistler > nvidia tegra20 > u8500_href arm armv7 u8500 > st-ericsson u8500 > snowball arm armv7 snowball > st-ericsson u8500 > +socfpga_cyclone5 arm armv7 socfpga_cyclone5 > altera socfpga > actux1_4_16 arm ixp actux1 - > - actux1:FLASH2X2 > actux1_4_32 arm ixp actux1 - > - actux1:FLASH2X2,RAM_32MB > actux1_8_16 arm ixp actux1 - > - actux1:FLASH1X8 > diff --git a/include/common.h b/include/common.h > index a7fb05e..ce9abaa 100644 > --- a/include/common.h > +++ b/include/common.h > @@ -582,7 +582,7 @@ int checkicache (void); > int checkdcache (void); > void upmconfig (unsigned int, unsigned int *, unsigned int); > ulong get_tbclk (void); > -void reset_cpu (ulong addr); > +void reset_cpu (ulong addr) __attribute__((noreturn)); > #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) > void ft_cpu_setup(void *blob, bd_t *bd); > #ifdef CONFIG_PCI > diff --git a/include/configs/socfpga_cyclone5.h > b/include/configs/socfpga_cyclone5.h > new file mode 100644 > index 0000000..d9eb5d9 > --- /dev/null > +++ b/include/configs/socfpga_cyclone5.h > @@ -0,0 +1,236 @@ > +/* > + * Copyright (C) 2012 Altera Corporation <www.altera.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#include <asm/arch/socfpga_base_addrs.h> > + > +/* > + * High level configuration > + */ > + > +#define CONFIG_ARMV7 > +#define CONFIG_L2_OFF > +#define CONFIG_SYS_DCACHE_OFF > +#undef CONFIG_USE_IRQ > + > +#define CONFIG_MISC_INIT_R > +#define CONFIG_SINGLE_BOOTLOADER > +#define CONFIG_SOCFPGA > + > +#define CONFIG_SYS_TEXT_BASE 0x08000040 > +#define V_NS16550_CLK 1000000 > +#define CONFIG_BAUDRATE 57600 > +#define CONFIG_SYS_HZ 1000 > +#define CONFIG_TIMER_CLOCK_KHZ 2400 > +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 > + > +/* Console I/O Buffer Size */ > +#define CONFIG_SYS_CBSIZE 256 > +/* Monitor Command Prompt */ > +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ > + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* > + * Display CPU and Board Info > + */ > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +/* > + * Enable early stage initialization at C environment > + */ > +#define CONFIG_BOARD_EARLY_INIT_F > + > +/* flat device tree */ > +#define CONFIG_OF_LIBFDT > +/* skip updating the FDT blob */ > +#define CONFIG_FDT_BLOB_SKIP_UPDATE > +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ > +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) > + > +#define CONFIG_SPL_RAM_DEVICE > +#define CONFIG_SPL_STACK (&__stack_start) > +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) > +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) > + > +/* > + * Memory allocation (MALLOC) > + */ > +/* Room required on the stack for the environment data */ > +#define CONFIG_ENV_SIZE 1024 > +/* Size of DRAM reserved for malloc() use */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) > + > +/* SP location before relocation, must use scratch RAM */ > +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 > +/* Reserving 0x100 space at back of scratch RAM for debug info */ > +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) > +/* Stack pointer prior relocation, must situated at on-chip RAM */ > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ > + CONFIG_SYS_INIT_RAM_SIZE - \ > + GENERATED_GBL_DATA_SIZE) > + > + > +/* > + * Command line configuration. > + */ > +#define CONFIG_SYS_NO_FLASH > +#include <config_cmd_default.h> > +/* FAT file system support */ > +#define CONFIG_CMD_FAT > + > + > +/* > + * Misc > + */ > +#define CONFIG_DOS_PARTITION 1 > + > +#ifdef CONFIG_SPL_BUILD > +#undef CONFIG_PARTITIONS > +#endif > + > +/* > + * Environment setup > + */ > + > +/* Delay before automatically booting the default image */ > +#define CONFIG_BOOTDELAY 3 > +/* Enable auto completion of commands using TAB */ > +#define CONFIG_AUTO_COMPLETE > +/* use "hush" command parser */ > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_CMD_RUN > + > +#define CONFIG_BOOTCOMMAND "run ramboot" > + > +/* > + * arguments passed to the bootm command. The value of > + * CONFIG_BOOTARGS goes into the environment value "bootargs". > + * Do note the value will overide also the chosen node in FDT blob. > + */ > +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "verify=n\0" \ > + "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ > + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ > + "bootm ${loadaddr} - ${fdt_addr}\0" \ > + "bootimage=uImage\0" \ > + "fdt_addr=100\0" \ > + "fsloadcmd=ext2load\0" \ > + "bootm ${loadaddr} - ${fdt_addr}\0" \ > + "qspiroot=/dev/mtdblock0\0" \ > + "qspirootfstype=jffs2\0" \ > + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ > + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ > + "bootm ${loadaddr} - ${fdt_addr}\0" > + > +/* using environment setting for stdin, stdout, stderr */ > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > +/* Enable the call to overwrite_console() */ > +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE > +/* Enable overwrite of previous console environment settings */ > +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE > + > +/* max number of command args */ > +#define CONFIG_SYS_MAXARGS 16 > + > + > +/* > + * Hardware drivers > + */ > + > +/* > + * SDRAM Memory Map > + */ > +/* We have 1 bank of DRAM */ > +#define CONFIG_NR_DRAM_BANKS 1 > +/* SDRAM Bank #1 */ > +#define CONFIG_SYS_SDRAM_BASE 0x00000000 > +/* SDRAM memory size */ > +#define PHYS_SDRAM_1_SIZE 0x80000000 > + > +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE > +#define CONFIG_SYS_MEMTEST_START 0x00000000 > +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE > + > +/* > + * NS16550 Configuration > + */ > +#define UART0_BASE SOCFPGA_UART0_ADDRESS > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE -4 > +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK > +#define CONFIG_CONS_INDEX 1 > +#define CONFIG_SYS_NS16550_COM1 UART0_BASE > + > +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} > + > +/* > + * FLASH > + */ > +#define CONFIG_SYS_NO_FLASH > + > +/* > + * L4 OSC1 Timer 0 > + */ > +/* This timer use eosc1 where the clock frequency is fixed > + * throughout any condition */ > +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS > + > +/* reload value when timer count to zero */ > +#define TIMER_LOAD_VAL 0xFFFFFFFF > + > +#define CONFIG_ENV_IS_NOWHERE > + > +/* > + * SPL "Second Program Loader" aka Initial Software > + */ > + > +/* Enable building of SPL globally */ > +#define CONFIG_SPL > +#define CONFIG_SPL_FRAMEWORK > + > +/* TEXT_BASE for linking the SPL binary */ > +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 > + > +/* Stack size for SPL */ > +#define CONFIG_SPL_STACK_SIZE (4 * 1024) > + > +/* MALLOC size for SPL */ > +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) > + > +#define CONFIG_SPL_SERIAL_SUPPORT > +#define CONFIG_SPL_BOARD_INIT > + > +#define CHUNKSZ_CRC32 (1 * 1024) > + > +#define CONFIG_CRC32_VERIFY > + > +/* Linker script for SPL */ > +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" > + > +/* Support for common/libcommon.o in SPL binary */ > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +/* Support for lib/libgeneric.o in SPL binary */ > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > + > +#endif /* __CONFIG_H */ Needs a V8... turning reset_cpu into a noreturn function causes warnings in other boards. Please either do not turn 'noreturn' or fix all resetcpu functions in the tree. Amicalement, -- Albert. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
