On 19/09/2012 20:32, Eric Nelson wrote: > Signed-off-by: Eric Nelson <[email protected]> > --- > arch/arm/include/asm/arch-mx6/imx-regs.h | 73 > ++++++++++++++++++++++++++++++ > 1 files changed, 73 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h > b/arch/arm/include/asm/arch-mx6/imx-regs.h > index 1781382..cb284e2 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -200,6 +200,79 @@ struct src { > u32 gpr10; > }; > > +struct iomuxc { > + u32 gpr[14]; > + u32 omux[5]; > + /* mux and pad registers */ > +}; > + > +#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20 > +#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK > (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET) > +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16 > +#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK > (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET) > + > +#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15 > +#define IOMUXC_GPR2_BGREF_RRMODE_MASK > (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) > +#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES > (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) > +#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES > (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET) > +#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0 > +#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1 > + > +#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10 > +#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK > (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) > +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH > (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) > +#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW > (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET) > + > +#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9 > +#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK > (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) > +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH > (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) > +#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW > (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET) > + > +#define IOMUXC_GPR2_BITMAP_SPWG 0 > +#define IOMUXC_GPR2_BITMAP_JEIDA 1 > + > +#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8 > +#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK > (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) > +#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA > (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) > +#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG > (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET) > + > +#define IOMUXC_GPR2_DATA_WIDTH_18 0 > +#define IOMUXC_GPR2_DATA_WIDTH_24 1 > + > +#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7 > +#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK > (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) > +#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT > (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) > +#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT > (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET) > + > +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 > +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK > (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) > +#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA > (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) > +#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG > (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET) > + > +#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5 > +#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK > (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) > +#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT > (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) > +#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT > (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET) > + > +#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4 > +#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK > (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET) > + > +#define IOMUXC_GPR2_MODE_DISABLED 0 > +#define IOMUXC_GPR2_MODE_ENABLED_DI0 1 > +#define IOMUXC_GPR2_MODE_ENABLED_DI1 2 > + > +#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2 > +#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK > (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED > (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 > (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 > (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET) > + > +#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0 > +#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK > (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED > (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 > (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) > +#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 > (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET) > + > /* ECSPI registers */ > struct cspi_regs { > u32 rxdata; >
Acked-by: Stefano Babic <[email protected]> Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected] ===================================================================== _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
