As explained in the PowerPC e500 Core Family Reference Manual
(Synchronization Requirements for SPRs), an isync instruction
is required after a mtspr mmucsr0 instruction.
Signed-off-by: Laurent Joye <laurent.j...@haslerrail.com>
---
arch/powerpc/cpu/mpc85xx/tlb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c
b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..c548f67 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -38,6 +38,7 @@ void invalidate_tlb(u8 tlb)
mtspr(MMUCSR0, 0x4);
if (tlb == 1)
mtspr(MMUCSR0, 0x2);
+ asm volatile("isync");
}
void init_tlbs(void)
--
1.7.10.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
