Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
Cc: Stefano Babic <sba...@denx.de>
---
.../arch/arm/cpu/armv7/imx-common/speed.c | 6 ---
.../arch/arm/cpu/armv7/mx5/clock.c | 52 ++++++++++++++++++++
.../arch/arm/include/asm/arch-mx5/clock.h | 4 ++
3 files changed, 56 insertions(+), 6 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/imx-common/speed.c
u-boot-4d3c95f/arch/arm/cpu/armv7/imx-common/speed.c
index 80989c4..d9cb7bc 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/imx-common/speed.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/imx-common/speed.c
@@ -34,12 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
-#ifdef CONFIG_FSL_USDHC
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#else
- gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
-#endif
-#endif
return 0;
}
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
index 0801e4f..a0339f6 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c
@@ -445,6 +445,50 @@ static u32 imx_get_cspiclk(void)
return ret_val;
}
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+ u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = __raw_readl(&mxc_ccm->cscdr1);
+
+ switch (port) {
+ case 0:
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+ pred = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
+ podf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET;
+ break;
+ case 1:
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET;
+ pred = (cscdr1 & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET;
+ podf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET;
+ break;
+ case 2:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ case 3:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ default:
+ break;
+ }
+
+ freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+ return freq;
+}
+
static u32 get_axi_a_clk(void)
{
u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
@@ -532,6 +576,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_uart_clk();
case MXC_CSPI_CLK:
return imx_get_cspiclk();
+ case MXC_ESDHC_CLK:
+ return get_esdhc_clk(0);
+ case MXC_ESDHC2_CLK:
+ return get_esdhc_clk(1);
+ case MXC_ESDHC3_CLK:
+ return get_esdhc_clk(2);
+ case MXC_ESDHC4_CLK:
+ return get_esdhc_clk(3);
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_SYS_MX5_HCLK);
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
index a03e61a..5eeca2a 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/clock.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/clock.h
@@ -31,6 +31,10 @@ enum mxc_clock {
MXC_IPG_PERCLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
MXC_FEC_CLK,
MXC_SATA_CLK,
MXC_DDR_CLK,
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