Set the spl mxc nand driver for IP 1.1 in symmetric mode, like the mtd driver.
In this way, for both drivers, one input clock period of the NFC IP will produce
one R/W cycle.
Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
Cc: Scott Wood <scottw...@freescale.com>
Cc: Stefano Babic <sba...@denx.de>
---
.../nand_spl/nand_boot_fsl_nfc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git u-boot-4d3c95f.orig/nand_spl/nand_boot_fsl_nfc.c
u-boot-4d3c95f/nand_spl/nand_boot_fsl_nfc.c
index 059969b..842943c 100644
--- u-boot-4d3c95f.orig/nand_spl/nand_boot_fsl_nfc.c
+++ u-boot-4d3c95f/nand_spl/nand_boot_fsl_nfc.c
@@ -57,7 +57,8 @@ static void nfc_nand_init(void)
writew(0x2, &nfc->config);
/* hardware ECC checking and correct */
- config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | NFC_FP_INT;
+ config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
+ NFC_ONE_CYCLE | NFC_FP_INT;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
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