On 10/08/2012 20:51, Benoît Thébaudeau wrote:
> Since the input frequency of the API is a maximum that should not be exceeded
> in
> order for the devices to operate properly, the SPI clock divider should be
> rounded up, not truncated.
>
Hi Benoît,
> Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
> Cc: Wolfgang Denk <w...@denx.de>
> Cc: Stefano Babic <sba...@denx.de>
> ---
> .../drivers/spi/mxc_spi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git u-boot-4d3c95f.orig/drivers/spi/mxc_spi.c
> u-boot-4d3c95f/drivers/spi/mxc_spi.c
> index 2e15318..cf1462f 100644
> --- u-boot-4d3c95f.orig/drivers/spi/mxc_spi.c
> +++ u-boot-4d3c95f/drivers/spi/mxc_spi.c
> @@ -96,7 +96,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned
> int cs,
>
> clk_src = mxc_get_clock(MXC_CSPI_CLK);
>
> - div = clk_src / max_hz;
> + div = DIV_ROUND_UP(clk_src, max_hz);
> div = get_cspi_div(div);
>
> debug("clk %d Hz, div %d, real clk %d Hz\n",
> @@ -147,7 +147,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs,
> unsigned int cs,
> * The following computation is taken directly from Freescale's code.
> */
> if (clk_src > max_hz) {
> - pre_div = clk_src / max_hz;
> + pre_div = DIV_ROUND_UP(clk_src, max_hz);
> if (pre_div > 16) {
> post_div = pre_div / 16;
> pre_div = 15;
>
Agree - do you also get a case where the divider was too low and the SPI
does not work or it was only examining the code ?
Acked-by: Stefano Babic <sba...@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=====================================================================
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
