On Tue, Jul 31, 2012 at 09:30:35AM +0000, Laurence Withers wrote: > On the DA830, UART2's clock is derived from PLL controller 0 output 2. > On the DA850, it is in the ASYNC3 group, and may be switched between PLL > controller 0 or 1. Fix the definition of the ID to match. > > Signed-off-by: Laurence Withers <lwith...@guralp.com> > Cc: Tom Rini <tr...@ti.com> > Cc: Prabhakar Lad <prabhakar.cse...@gmail.com>
I've applied this after making it apply cleanly again (DAVINCI_MMC0_CLKID again), thanks! -- Tom
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