[U-Boot] [PATCH 1/7 V4] EXYNOS5: Add pinmux support for SPI

[Rajeshwari Shinde]

This patch adds pinmux support for SPI channels

Signed-off-by: Rajeshwari Shinde <rajeshwar...@samsung.com>
---
Changes in V2:
        - None.
Changes in V3:
        - Removed the slave flag for SPI.
Changes in V4:
        - Rebased on Mainline u-boot.git.
 arch/arm/cpu/armv7/exynos/pinmux.c        |   51 ++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-exynos/periph.h |    5 +++
 2 files changed, 55 insertions(+), 1 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index d28f055..415d7fa 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -226,6 +226,49 @@ static void exynos5_i2c_config(int peripheral, int flags)
        }
 }
 
+void exynos5_spi_config(int peripheral)
+{
+       int cfg = 0, pin = 0, i;
+       struct s5p_gpio_bank *bank = NULL;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct exynos5_gpio_part2 *gpio2 =
+               (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+       switch (peripheral) {
+       case PERIPH_ID_SPI0:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI1:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 4;
+               break;
+       case PERIPH_ID_SPI2:
+               bank = &gpio1->b1;
+               cfg = GPIO_FUNC(0x5);
+               pin = 1;
+               break;
+       case PERIPH_ID_SPI3:
+               bank = &gpio2->f1;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI4:
+               for (i = 2; i < 4; i++)
+                       s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4));
+               for (i = 4; i < 6; i++)
+                       s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4));
+               break;
+       }
+       if (peripheral != PERIPH_ID_SPI4) {
+               for (i = pin; i < pin + 4; i++)
+                       s5p_gpio_cfg_pin(bank, i, cfg);
+       }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -253,11 +296,17 @@ static int exynos5_pinmux_config(int peripheral, int 
flags)
        case PERIPH_ID_I2C7:
                exynos5_i2c_config(peripheral, flags);
                break;
+       case PERIPH_ID_SPI0:
+       case PERIPH_ID_SPI1:
+       case PERIPH_ID_SPI2:
+       case PERIPH_ID_SPI3:
+       case PERIPH_ID_SPI4:
+               exynos5_spi_config(peripheral);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
        }
-
        return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-exynos/periph.h 
b/arch/arm/include/asm/arch-exynos/periph.h
index b861d7d..dafc3f3 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -43,6 +43,11 @@ enum periph_id {
        PERIPH_ID_SDMMC2,
        PERIPH_ID_SDMMC3,
        PERIPH_ID_SROMC,
+       PERIPH_ID_SPI0,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SPI3,
+       PERIPH_ID_SPI4,
        PERIPH_ID_UART0,
        PERIPH_ID_UART1,
        PERIPH_ID_UART2,
-- 
1.7.4.4

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