This patch starts series of patches adding support for USB support on PXA255 chips.
Signed-off-by: Łukasz Dałek <luk0...@gmail.com> --- arch/arm/include/asm/arch-pxa/pxa-regs.h | 247 ++++++++++++++++++++++++++++++ 1 files changed, 247 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index b81b42c..114e9a2 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -2498,6 +2498,253 @@ typedef void (*ExcpHndlr) (void) ; #endif /* CONFIG_CPU_PXA27X */ +#if defined(CONFIG_CPU_PXA25X) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCR *((volatile u32 *)0x40600000) +#else +# define UDCCR 0x40600000 +#endif + +#define UDCCR_UDE (1 << 0) +#define UDCCR_UDA (1 << 1) +#define UDCCR_RSM (1 << 2) +#define UDCCR_RESIR (1 << 3) +#define UDCCR_SUSIR (1 << 4) +#define UDCCR_SRM (1 << 5) +#define UDCCR_RSTIR (1 << 6) +#define UDCCR_REM (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCFR *((volatile u32 *)0x40600008) +#else +# define UDCCFR 0x40600008 +#endif + +#define UDCCFR_AREN (1 << 7) +#define UDCCFR_ACM (1 << 2) +#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UICR0 *((volatile u32 *)0x40600050) +#else +# define UICR0 0x40600050 +#endif + +#define UICR0_MASK 0xf +#define UICR0_IM0 (1 << 0) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UICR1 *((volatile u32 *)0x40600054) +#else +# define UICR1 0x40600054 +#endif + +#define UICR1_MASK 0xf + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define USIR0 *((volatile u32 *)0x40600058) +#else +# define USIR0 0x40600058 +#endif + +#define USIR0_MASK 0xf +#define USIR0_IR0 (1 << 0) +#define USIR0_IR1 (1 << 1) +#define USIR0_IR2 (1 << 2) +#define USIR0_IR3 (1 << 3) +#define USIR0_IR4 (1 << 4) +#define USIR0_IR5 (1 << 5) +#define USIR0_IR6 (1 << 6) +#define USIR0_IR7 (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define USIR1 *((volatile u32 *)0x4060005c) +#else +# define USIR1 0x4060005c +#endif + +#define USIR1_MASK 0xf +#define USIR1_IR8 (1 << 0) +#define USIR1_IR9 (1 << 1) +#define USIR1_IR10 (1 << 2) +#define USIR1_IR11 (1 << 3) +#define USIR1_IR12 (1 << 4) +#define USIR1_IR13 (1 << 5) +#define USIR1_IR14 (1 << 6) +#define USIR1_IR15 (1 << 7) + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDCCS0 *((volatile u32 *)0x40600010) +# define UDCCS1 *((volatile u32 *)0x40600014) +# define UDCCS2 *((volatile u32 *)0x40600018) +# define UDCCS3 *((volatile u32 *)0x4060001c) +# define UDCCS4 *((volatile u32 *)0x40600020) +# define UDCCS5 *((volatile u32 *)0x40600024) +# define UDCCS6 *((volatile u32 *)0x40600028) +# define UDCCS7 *((volatile u32 *)0x4060002c) +# define UDCCS8 *((volatile u32 *)0x40600030) +# define UDCCS9 *((volatile u32 *)0x40600034) +# define UDCCS10 *((volatile u32 *)0x40600038) +# define UDCCS11 *((volatile u32 *)0x4060003c) +# define UDCCS12 *((volatile u32 *)0x40600040) +# define UDCCS13 *((volatile u32 *)0x40600044) +# define UDCCS14 *((volatile u32 *)0x40600048) +# define UDCCS15 *((volatile u32 *)0x4060004c) +#else +# define UDCCS(x) (0x40600010 + 4 * (x)) +# define UDCCS0 UDCCS(0) +#endif + +/* Control endpoint 0 */ +#define UDCCS_CTRL_OPR (1 << 0) +#define UDCCS_CTRL_IPR (1 << 1) +#define UDCCS_CTRL_FTF (1 << 2) +#define UDCCS_CTRL_DRWF (1 << 3) +#define UDCCS_CTRL_SST (1 << 4) +#define UDCCS_CTRL_FST (1 << 5) +#define UDCCS_CTRL_RNE (1 << 6) +#define UDCCS_CTRL_SA (1 << 7) + +/* Linux compat */ +#define UDCCS0_SA UDCCS_CTRL_SA +#define UDCCS0_RNE UDCCS_CTRL_RNE +#define UDCCS0_FST UDCCS_CTRL_FST +#define UDCCS0_SST UDCCS_CTRL_SST +#define UDCCS0_DRWF UDCCS_CTRL_DRWF +#define UDCCS0_FTF UDCCS_CTRL_FTF +#define UDCCS0_IPR UDCCS_CTRL_IPR +#define UDCCS0_OPR UDCCS_CTRL_OPR + +/* Bulk IN endpoint 1/6/11 */ +#define UDCCS_BULK_IN_TSP (1 << 7) +#define UDCCS_BULK_IN_FST (1 << 5) +#define UDCCS_BULK_IN_SST (1 << 4) +#define UDCCS_BULK_IN_TUR (1 << 3) +#define UDCCS_BULK_IN_FTF (1 << 2) +#define UDCCS_BULK_IN_TPC (1 << 1) +#define UDCCS_BULK_IN_TFS (1 << 0) + +/* Linux compat */ +#define UDCCS_BI_TFS UDCCS_BULK_IN_TFS +#define UDCCS_BI_TPC UDCCS_BULK_IN_TPC +#define UDCCS_BI_FTF UDCCS_BULK_IN_FTF +#define UDCCS_BI_TUR UDCCS_BULK_IN_TUR +#define UDCCS_BI_SST UDCCS_BULK_IN_SST +#define UDCCS_BI_FST UDCCS_BULK_IN_FST +#define UDCCS_BI_TSP UDCCS_BULK_IN_TSP + +/* Bulk OUT endpoint 2/7/12 */ +#define UDCCS_BULK_OUT_RSP (1 << 7) +#define UDCCS_BULK_OUT_RNE (1 << 6) +#define UDCCS_BULK_OUT_FST (1 << 5) +#define UDCCS_BULK_OUT_SST (1 << 4) +#define UDCCS_BULK_OUT_DME (1 << 3) +#define UDCCS_BULK_OUT_RPC (1 << 1) +#define UDCCS_BULK_OUT_RFS (1 << 0) + +/* Linux compat */ +#define UDCCS_BO_RSP UDCCS_BULK_OUT_RSP +#define UDCCS_BO_RNE UDCCS_BULK_OUT_RNE +#define UDCCS_BO_FST UDCCS_BULK_OUT_FST +#define UDCCS_BO_SST UDCCS_BULK_OUT_SST +#define UDCCS_BO_DME UDCCS_BULK_OUT_DME +#define UDCCS_BO_RPC UDCCS_BULK_OUT_RPC +#define UDCCS_BO_RFS UDCCS_BULK_OUT_RFS + +/* Isochronous IN endpoint 3/8/13 */ +#define UDCCS_ISO_IN_TSP (1 << 7) +#define UDCCS_ISO_IN_TUR (1 << 3) +#define UDCCS_ISO_IN_FTF (1 << 2) +#define UDCCS_ISO_IN_TPC (1 << 1) +#define UDCCS_ISO_IN_TFS (1 << 0) + +/* Isochronous OUT endpoint 4/9/14 */ +#define UDCCS_ISO_OUT_RSP (1 << 7) +#define UDCCS_ISO_OUT_RNE (1 << 6) +#define UDCCS_ISO_OUT_DME (1 << 3) +#define UDCCS_ISO_OUT_ROF (1 << 2) +#define UDCCS_ISO_OUT_RPC (1 << 1) +#define UDCCS_ISO_OUT_RFS (1 << 0) + +/* Linux compat */ +#define UDCCS_IO_RSP UDCCS_ISO_OUT_RSP +#define UDCCS_IO_RNE UDCCS_ISO_OUT_RNE +#define UDCCS_IO_DME UDCCS_ISO_OUT_DME +#define UDCCS_IO_ROF UDCCS_ISO_OUT_ROF +#define UDCCS_IO_RPC UDCCS_ISO_OUT_RPC +#define UDCCS_IO_RFS UDCCS_ISO_OUT_RFS + +/* Interrupt IN endpoint 5/10/15 */ +#define UDCCS_INT_TSP (1 << 7) +#define UDCCS_INT_FST (1 << 5) +#define UDCCS_INT_SST (1 << 4) +#define UDCCS_INT_TUR (1 << 3) +#define UDCCS_INT_FTF (1 << 2) +#define UDCCS_INT_TPC (1 << 1) +#define UDCCS_INT_TFS (1 << 0) + +/* Byte count registers */ +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UBCR2 *((volatile u32 *)0x40600068) +# define UBCR4 *((volatile u32 *)0x4060006c) +# define UBCR7 *((volatile u32 *)0x40600070) +# define UBCR9 *((volatile u32 *)0x40600074) +# define UBCR12 *((volatile u32 *)0x40600078) +# define UBCR14 *((volatile u32 *)0x4060007c) +#else +# define UBCR2 0x40600068 +# define UBCR4 0x4060006c +# define UBCR7 0x40600070 +# define UBCR9 0x40600074 +# define UBCR12 0x40600078 +# define UBCR14 0x4060007c +#endif + +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UDDR0 *((volatile u32 *)0x40600080) +# define UDDR1 *((volatile u32 *)0x40600100) +# define UDDR2 *((volatile u32 *)0x40600180) +# define UDDR3 *((volatile u32 *)0x40600200) +# define UDDR4 *((volatile u32 *)0x40600400) +# define UDDR5 *((volatile u32 *)0x406000A0) +# define UDDR6 *((volatile u32 *)0x40600600) +# define UDDR7 *((volatile u32 *)0x40600680) +# define UDDR8 *((volatile u32 *)0x40600700) +# define UDDR9 *((volatile u32 *)0x40600900) +# define UDDR10 *((volatile u32 *)0x406000C0) +# define UDDR11 *((volatile u32 *)0x40600B00) +# define UDDR12 *((volatile u32 *)0x40600B80) +# define UDDR13 *((volatile u32 *)0x40600C00) +# define UDDR14 *((volatile u32 *)0x40600E00) +# define UDDR15 *((volatile u32 *)0x406000E0) +#else +# define UDDR0 0x40600080 +# define UDDR1 0x40600100 +# define UDDR2 0x40600180 +# define UDDR3 0x40600200 +# define UDDR4 0x40600400 +# define UDDR5 0x406000A0 +# define UDDR6 0x40600600 +# define UDDR7 0x40600680 +# define UDDR8 0x40600700 +# define UDDR9 0x40600900 +# define UDDR10 0x406000C0 +# define UDDR11 0x40600B00 +# define UDDR12 0x40600B80 +# define UDDR13 0x40600C00 +# define UDDR14 0x40600E00 +# define UDDR15 0x406000E0 +#endif + +/* Linux compat */ +#ifdef CONFIG_PXA25X_UDC_LINUX +# define UFNRH *((volatile u32 *)0x40600060) +# define UFNRL *((volatile u32 *)0x40600064) +#endif + +#endif /* CONFIG_CPU_PXA25X */ + /* LCD registers */ #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ #define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ -- 1.7.3.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
