Dear mathieu.poir...@linaro.org,
In message <1341413915-7944-12-git-send-email-mathieu.poir...@linaro.org> you
wrote:
> From: "Mathieu J. Poirier" <mathieu.poir...@linaro.org>
>
> Following ARM's reference manuel for initializing the cache - the
> kernel won't boot otherwise.
>
> Signed-off-by: Mathieu Poirier <mathieu.poir...@linaro.org>
> Signed-off-by: John Rigby <john.ri...@linaro.org>
> ---
> Changes for v2:
> - Correcting cache maintenance register address.
> - Invalidating all 16 bits in cache maintenance register.
> - Polling cache maintenance register for cleared bits.
> - Added comments to the code.
> - Re-worked commit description.
> ---
> arch/arm/cpu/armv7/u8500/cpu.c | 16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
...
> +void cpu_cache_initialization(void)
> +{
> + /* invalidate all cache entries */
> + *((volatile unsigned int *)(0xA041277C)) = 0xFFFF;
...
> + while (*((volatile unsigned int *)(0xA041277C)) & 0xFF)
...
> + *((volatile unsigned int *)(0xA0412900)) = 0xFF;
> + *((volatile unsigned int *)(0xA0412904)) = 0xFF;
NAK. Please use proper I/O accessors, and declare a C struct to
access these registers.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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wartet!"
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