On 06/25/2012 06:37 PM, Marek Vasut wrote: > Dear Scott Wood, > >> On 06/24/2012 07:17 PM, Marek Vasut wrote: >>> This prevents the scenario where data cache is on and the >>> device uses DMA to deploy data. In that case, it might not >>> be possible to flush/invalidate data to RAM properly. The >>> other option is to use bounce buffer, >> >> Or get cache coherent hardware. :-) > > Oh ... you mean powerpc? Or rather something like this > http://cache.freescale.com/files/32bit/doc/fact_sheet/QORIQLS2FAMILYFS.pdf ? > :-D
The word "coherent/coherency" appears 5 times in that document by my count. :-) I hope that applies to DMA, not just core-to-core. >>> but that involves a lot of copying and therefore degrades performance >>> rapidly. Therefore disallow this possibility of unaligned load >>> address altogether if data cache is on. >> >> How about use the bounce buffer only if the address is misaligned? > > Not happening, bounce buffer is bullshit, Hacking up the common frontend with a new limitation because you can't be bothered to fix your drivers is bullshit. > It's like driving a car in the wrong lane. Sure, you can do it, but it'll > eventually have some consequences. And using a bounce buffer is like driving > a > tank in the wrong lane ... Using a bounce buffer is like parking your car before going into the building, rather than insisting the building's hallways be paved. >> The >> corrective action a user has to take is the same as with this patch, >> except for an additional option of living with the slight performance >> penalty. > > Slight is very weak word here. Prove me wrong with benchmarks. >> How often does this actually happen? How much does it >> actually slow things down compared to the speed of the NAND chip? > > If the user is dumb, always. But if you tell the user how to milk the most of > the hardware, he'll be happier. So, if you use bounce buffers conditionally (based on whether the address is misaligned), there's no impact except to "dumb" users, and for those users they would merely get a performance degradation rather than breakage. How is this "bullshit"? >> I'm hesitant to break something -- even if it's odd (literally in this >> case) -- that currently works on most hardware, just because one or two >> drivers can't handle it. It feels kind of like changing the read() and >> write() system calls to require cacheline alignment. :-P > > That's actually almost right, we're doing a bootloader here, it might have > limitations. We're not writing yet another operating system with no bounds on > possibilities! We also don't need to bend over backwards to squeeze every last cycle out of the boot process, at the expense of a stable user interface (not to mention requiring the user to know the system's cache line size). -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
