On Wed, May 30, 2012 at 10:46:00AM -0700, Steve Sakoman wrote: > The PLL setup values currently assume a 24 Mhz input clock. > > This patch uses V_OSCK from the board config file to support boards > with different input clock rates. > > Signed-off-by: Steve Sakoman <st...@sakoman.com>
Queued up for u-boot-ti/master, thanks! -- Tom
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