>-----Original Message----- >From: Dirk Behme [mailto:dirk.be...@de.bosch.com] >Sent: Tuesday, June 12, 2012 11:05 PM >To: Fabio Estevam; Liu Hui-R64343 >Cc: Vikram Narayanan; u-boot@lists.denx.de >Subject: Re: [U-Boot] [PATCH] mx6: Avoid writing to read-only bits in >imximage.cfg > >On 12.06.2012 16:50, Vikram Narayanan wrote: >> If in case this is valid according to the latest datasheet, ignore this >> patch. > > >> -- >> According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 >> and 5 read-only and the value is always set as zero. >> So write '0' to these bits instead of writing '1'. > >Jason, Fabio: What do you think? You should be the datasheet 'masters' ;)
Yes, according to the RM, 5 Reserved This read-only field is reserved and always has the value 0. 4 Reserved This read-only field is reserved and always has the value 0. So, write 1 should have no effect. > >Best regards > >Dirk > > >> Signed-off-by: Vikram Narayanan <vikram...@gmail.com> >> Cc: Jason Liu <r64...@freescale.com> >> Cc: Dirk Behme <dirk.be...@googlemail.com> >> --- >> board/freescale/mx6qarm2/imximage.cfg | 2 +- >> board/freescale/mx6qsabrelite/imximage.cfg | 2 +- >> 2 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/board/freescale/mx6qarm2/imximage.cfg >> b/board/freescale/mx6qarm2/imximage.cfg >> index ceecbf9..bf941a3 100644 >> --- a/board/freescale/mx6qarm2/imximage.cfg >> +++ b/board/freescale/mx6qarm2/imximage.cfg >> @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 >0x020c4080 >> 0x000003FF >> >> # enable AXI cache for VDOA/VPU/IPU >> -DATA 4 0x020e0010 0xF00000FF >> +DATA 4 0x020e0010 0xF00000CF >> # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 >> 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git >> a/board/freescale/mx6qsabrelite/imximage.cfg >> b/board/freescale/mx6qsabrelite/imximage.cfg >> index c389427..62498ab 100644 >> --- a/board/freescale/mx6qsabrelite/imximage.cfg >> +++ b/board/freescale/mx6qsabrelite/imximage.cfg >> @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 >0x020c4080 >> 0x000003FF >> >> # enable AXI cache for VDOA/VPU/IPU >> -DATA 4 0x020e0010 0xF00000FF >> +DATA 4 0x020e0010 0xF00000CF >> # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 >> 0x007F007F DATA 4 0x020e001c 0x007F007F _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
