Hi,
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwar...@samsung.com
> wrote:
> Add pinmux support for SDMMC4 on EXYNOS5.
>
> Signed-off-by: Terry Lambert <tlamb...@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwar...@samsung.com>
>
Is this relevant only to EVT0? It's fine if this is just a step along the
way, just wanted to check.
> ---
> This patch is based on:
> "EXYNOS5: PINMUX: Added default pinumx settings"
> arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++-------
> 1 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index 103bcbb..9319fd6 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags)
> struct exynos5_gpio_part1 *gpio1 =
> (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
> struct s5p_gpio_bank *bank, *bank_ext;
> - int i, start, count;
> + int i, start, count, pin, pin_ext, drv;
>
> switch (peripheral) {
> case PERIPH_ID_UART0:
> @@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags)
> case PERIPH_ID_SDMMC1:
> case PERIPH_ID_SDMMC2:
> case PERIPH_ID_SDMMC3:
> + case PERIPH_ID_SDMMC4:
> + pin = GPIO_FUNC(0x2);
> + pin_ext = GPIO_FUNC(0x3);
> + drv = GPIO_DRV_4X;
> switch (peripheral) {
> case PERIPH_ID_SDMMC0:
> bank = &gpio1->c0; bank_ext = &gpio1->c1;
> @@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags)
> case PERIPH_ID_SDMMC3:
> bank = &gpio1->c3; bank_ext = NULL;
> break;
> + case PERIPH_ID_SDMMC4:
> + bank = &gpio1->c0; bank_ext = &gpio1->c1;
> + pin = GPIO_FUNC(0x3);
> + pin_ext = GPIO_FUNC(0x4);
> + drv = GPIO_DRV_2X;
> + break;
> }
> if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
> debug("SDMMC device %d does not support 8bit mode",
> @@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags)
> }
> if (flags & PINMUX_FLAG_8BIT_MODE) {
> for (i = 3; i <= 6; i++) {
> - s5p_gpio_cfg_pin(bank_ext, i,
> GPIO_FUNC(0x3));
> + s5p_gpio_cfg_pin(bank_ext, i, pin_ext);
> s5p_gpio_set_pull(bank_ext, i,
> GPIO_PULL_UP);
> - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
> + s5p_gpio_set_drv(bank_ext, i, drv);
> }
> }
> for (i = 0; i < 2; i++) {
> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(bank, i, pin);
> s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
> + s5p_gpio_set_drv(bank, i, drv);
> }
> for (i = 3; i <= 6; i++) {
> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
> + s5p_gpio_cfg_pin(bank, i, pin);
> s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
> + s5p_gpio_set_drv(bank, i, drv);
> }
> break;
> case PERIPH_ID_SROMC:
> --
> 1.7.4.4
>
> Regards,
Simon
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