On 05/23/2012 05:22 AM, R, Sricharan wrote:
Hi Tom,
ah, this is what is there on OMAP5.
3 for DDR3
4 for LPDDR2-S4,
5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2
in same way.
Is the reset value set correctly on am335x according to the device
connected?
I'll have to do some checking as the code doesn't check that today.
The reset value reflects the connected device correctly for lpddr2 and ddr3.
Is that the same case in am33xx platforms ?
Yes, it's 3 on DDR3 and 2 on (non-LP) DDR2. I spent some time yesterday
starting on splitting up emif-common (am33xx does not have DMM) and
making am33xx link at least with the common code. My idea is to add a
few more defines and make that part of do_sdram_init be:
if (!in_sdram) {
switch(reg_sdram_type) {
#ifdef CONFIG_EMIF4_DDR2
case 2:
ddr2_init();
break;
#ifdef CONFIG_EMFI4_DDR3
case 3:
ddr3_init();
break;
#endif
#ifdef CONFIG_EMIF4_LPDDR2
case 4:
case 5:
lpddr2_init();
break;
#endif
default:
panic("Unsupported DDR type connected to EMIF4");
}
}
And move lpddr2_init to emif4-lpddr2.c, and so forth. My experimenting
yesterday lead me to conclude that EMIF_MOD_ID_REGISTER behaves as is
documented for am33xx on omap4/5 so what we're doing should be feasible.
I'm going to try and locally make the ddr3 patches work on the am33xx
DDR3 board as a way to prove that out and if it works, and we're fine
with what I've laid out above, start working towards that layout.
--
Tom
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