---
board/davinci/dm365evm/dm365evm.c | 68 ++++++++++++++++++++++++++++++++++++
include/configs/davinci_dm365evm.h | 11 ++++++
2 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/board/davinci/dm365evm/dm365evm.c
b/board/davinci/dm365evm/dm365evm.c
index ac54106..fb05019 100644
--- a/board/davinci/dm365evm/dm365evm.c
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -150,3 +150,71 @@ int board_mmc_init(bd_t *bis)
return err;
}
#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+static struct davinci_timer * const wdttimer =
+ (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
+
+/* WDTCR bit definitions */
+#define WDEN (1 << 14)
+#define WDFLAG (1 << 15)
+#define WDKEY_SEQ0 (0xa5c6 << 16)
+#define WDKEY_SEQ1 (0xda7e << 16)
+
+/* TCR bit definitions */
+#define ENAMODE12_DISABLED (0 << 6)
+#define ENAMODE12_ONESHOT (1 << 6)
+#define ENAMODE12_PERIODIC (2 << 6)
+
+/* TGCR bit definitions */
+#define TIM12RS_UNRESET (1 << 0)
+#define TIM34RS_UNRESET (1 << 1)
+#define TIMMODE_64BIT_WDOG (2 << 2)
+
+static void _hw_watchdog_enable(void)
+{
+ u32 timer_margin;
+ ulong wdt_freq;
+
+ /* disable, internal clock source */
+ writel(0x0, &wdttimer->tcr);
+ /* reset timer, set mode to 64-bit watchdog, and unreset */
+ writel(0x0, &wdttimer->tgcr);
+ writel(TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET,
&wdttimer->tgcr);
+ /* clear counter regs */
+ writel(0x0, &wdttimer->tim12);
+ writel(0x0, &wdttimer->tim34);
+
+ /* set timeout period */
+ wdt_freq = CONFIG_SYS_HZ_CLOCK;
+ printf("Setting watchdog period to %llu ticks == %is *
%luHz\n",((u64)CONFIG_SYS_WDT_PERIOD_SECONDS * wdt_freq),
CONFIG_SYS_WDT_PERIOD_SECONDS, wdt_freq);
+ timer_margin = (((u64)CONFIG_SYS_WDT_PERIOD_SECONDS * wdt_freq) &
0xffffffff);
+ writel(timer_margin, &wdttimer->prd12);
+ timer_margin = (((u64)CONFIG_SYS_WDT_PERIOD_SECONDS * wdt_freq) >> 32);
+ writel(timer_margin, &wdttimer->prd34);
+
+ /* enable run continuously */
+ writel(ENAMODE12_PERIODIC, &wdttimer->tcr);
+
+ /* put watchdog in pre-active state */
+ writel(WDKEY_SEQ0 | WDEN, &wdttimer->wdtcr);
+ /* put watchdog in active state */
+ writel(WDKEY_SEQ1 | WDEN, &wdttimer->wdtcr);
+}
+
+void hw_watchdog_reset(void)
+{
+ writel(WDKEY_SEQ0, &wdttimer->wdtcr);
+ writel(WDKEY_SEQ1, &wdttimer->wdtcr);
+}
+
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ _hw_watchdog_enable();
+#endif
+ return 0;
+}
+
diff --git a/include/configs/davinci_dm365evm.h
b/include/configs/davinci_dm365evm.h
index a75bce6..04173b9 100644
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -245,4 +245,15 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_MISC_INIT_R
+
+// Hardware watchdog config
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE 0x01C21C00
+#define CONFIG_SYS_WDT_PERIOD_SECONDS 60
+// These two are insignificant but required to build
arch/arm/cpu/arm926ejs/davinci/timer.c
+#define CONFIG_SYS_WDT_PERIOD_LOW 0
+#define CONFIG_SYS_WDT_PERIOD_HIGH 0
+#endif
+
#endif /* __CONFIG_H */
--
1.7.0.4
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